1*56449d20SBin Meng /* 2*56449d20SBin Meng * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface 3*56449d20SBin Meng * 4*56449d20SBin Meng * Copyright (c) 2017 SiFive, Inc. 5*56449d20SBin Meng * 6*56449d20SBin Meng * This program is free software; you can redistribute it and/or modify it 7*56449d20SBin Meng * under the terms and conditions of the GNU General Public License, 8*56449d20SBin Meng * version 2 or later, as published by the Free Software Foundation. 9*56449d20SBin Meng * 10*56449d20SBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 11*56449d20SBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12*56449d20SBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13*56449d20SBin Meng * more details. 14*56449d20SBin Meng * 15*56449d20SBin Meng * You should have received a copy of the GNU General Public License along with 16*56449d20SBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 17*56449d20SBin Meng */ 18*56449d20SBin Meng 19*56449d20SBin Meng #ifndef HW_SIFIVE_E_PRCI_H 20*56449d20SBin Meng #define HW_SIFIVE_E_PRCI_H 21*56449d20SBin Meng 22*56449d20SBin Meng enum { 23*56449d20SBin Meng SIFIVE_E_PRCI_HFROSCCFG = 0x0, 24*56449d20SBin Meng SIFIVE_E_PRCI_HFXOSCCFG = 0x4, 25*56449d20SBin Meng SIFIVE_E_PRCI_PLLCFG = 0x8, 26*56449d20SBin Meng SIFIVE_E_PRCI_PLLOUTDIV = 0xC 27*56449d20SBin Meng }; 28*56449d20SBin Meng 29*56449d20SBin Meng enum { 30*56449d20SBin Meng SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31), 31*56449d20SBin Meng SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30) 32*56449d20SBin Meng }; 33*56449d20SBin Meng 34*56449d20SBin Meng enum { 35*56449d20SBin Meng SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31), 36*56449d20SBin Meng SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30) 37*56449d20SBin Meng }; 38*56449d20SBin Meng 39*56449d20SBin Meng enum { 40*56449d20SBin Meng SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16), 41*56449d20SBin Meng SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17), 42*56449d20SBin Meng SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18), 43*56449d20SBin Meng SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31) 44*56449d20SBin Meng }; 45*56449d20SBin Meng 46*56449d20SBin Meng enum { 47*56449d20SBin Meng SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8) 48*56449d20SBin Meng }; 49*56449d20SBin Meng 50*56449d20SBin Meng #define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" 51*56449d20SBin Meng 52*56449d20SBin Meng #define SIFIVE_E_PRCI(obj) \ 53*56449d20SBin Meng OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI) 54*56449d20SBin Meng 55*56449d20SBin Meng typedef struct SiFiveEPRCIState { 56*56449d20SBin Meng /*< private >*/ 57*56449d20SBin Meng SysBusDevice parent_obj; 58*56449d20SBin Meng 59*56449d20SBin Meng /*< public >*/ 60*56449d20SBin Meng MemoryRegion mmio; 61*56449d20SBin Meng uint32_t hfrosccfg; 62*56449d20SBin Meng uint32_t hfxosccfg; 63*56449d20SBin Meng uint32_t pllcfg; 64*56449d20SBin Meng uint32_t plloutdiv; 65*56449d20SBin Meng } SiFiveEPRCIState; 66*56449d20SBin Meng 67*56449d20SBin Meng DeviceState *sifive_e_prci_create(hwaddr addr); 68*56449d20SBin Meng 69*56449d20SBin Meng #endif 70