1 /* 2 * Nuvoton NPCM7xx/8xx System Global Control Registers. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 #ifndef NPCM_GCR_H 17 #define NPCM_GCR_H 18 19 #include "exec/memory.h" 20 #include "hw/sysbus.h" 21 #include "qom/object.h" 22 23 /* 24 * NPCM7XX PWRON STRAP bit fields 25 * 12: SPI0 powered by VSBV3 at 1.8V 26 * 11: System flash attached to BMC 27 * 10: BSP alternative pins. 28 * 9:8: Flash UART command route enabled. 29 * 7: Security enabled. 30 * 6: HI-Z state control. 31 * 5: ECC disabled. 32 * 4: Reserved 33 * 3: JTAG2 enabled. 34 * 2:0: CPU and DRAM clock frequency. 35 */ 36 #define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12) 37 #define NPCM7XX_PWRON_STRAP_SFAB BIT(11) 38 #define NPCM7XX_PWRON_STRAP_BSPA BIT(10) 39 #define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8) 40 #define FUP_NORM_UART2 3 41 #define FUP_PROG_UART3 2 42 #define FUP_PROG_UART2 1 43 #define FUP_NORM_UART3 0 44 #define NPCM7XX_PWRON_STRAP_SECEN BIT(7) 45 #define NPCM7XX_PWRON_STRAP_HIZ BIT(6) 46 #define NPCM7XX_PWRON_STRAP_ECC BIT(5) 47 #define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4) 48 #define NPCM7XX_PWRON_STRAP_J2EN BIT(3) 49 #define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x) 50 #define CKFRQ_SKIPINIT 0x000 51 #define CKFRQ_DEFAULT 0x111 52 53 /* 54 * Number of registers in our device state structure. Don't change this without 55 * incrementing the version_id in the vmstate. 56 */ 57 #define NPCM_GCR_MAX_NR_REGS NPCM8XX_GCR_NR_REGS 58 #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t)) 59 #define NPCM8XX_GCR_NR_REGS (0xf80 / sizeof(uint32_t)) 60 61 typedef struct NPCMGCRState { 62 SysBusDevice parent; 63 64 MemoryRegion iomem; 65 66 uint32_t regs[NPCM_GCR_MAX_NR_REGS]; 67 68 uint32_t reset_pwron; 69 uint32_t reset_mdlr; 70 uint32_t reset_intcr3; 71 uint32_t reset_scrpad_b; 72 } NPCMGCRState; 73 74 typedef struct NPCMGCRClass { 75 SysBusDeviceClass parent; 76 77 size_t nr_regs; 78 const uint32_t *cold_reset_values; 79 } NPCMGCRClass; 80 81 #define TYPE_NPCM_GCR "npcm-gcr" 82 #define TYPE_NPCM7XX_GCR "npcm7xx-gcr" 83 #define TYPE_NPCM8XX_GCR "npcm8xx-gcr" 84 OBJECT_DECLARE_TYPE(NPCMGCRState, NPCMGCRClass, NPCM_GCR) 85 86 #endif /* NPCM_GCR_H */ 87