1e5a7ba87SHavard Skinnemoen /* 2e5a7ba87SHavard Skinnemoen * Nuvoton NPCM7xx System Global Control Registers. 3e5a7ba87SHavard Skinnemoen * 4e5a7ba87SHavard Skinnemoen * Copyright 2020 Google LLC 5e5a7ba87SHavard Skinnemoen * 6e5a7ba87SHavard Skinnemoen * This program is free software; you can redistribute it and/or modify it 7e5a7ba87SHavard Skinnemoen * under the terms of the GNU General Public License as published by the 8e5a7ba87SHavard Skinnemoen * Free Software Foundation; either version 2 of the License, or 9e5a7ba87SHavard Skinnemoen * (at your option) any later version. 10e5a7ba87SHavard Skinnemoen * 11e5a7ba87SHavard Skinnemoen * This program is distributed in the hope that it will be useful, but WITHOUT 12e5a7ba87SHavard Skinnemoen * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13e5a7ba87SHavard Skinnemoen * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14e5a7ba87SHavard Skinnemoen * for more details. 15e5a7ba87SHavard Skinnemoen */ 16*506af233SHao Wu #ifndef NPCM_GCR_H 17*506af233SHao Wu #define NPCM_GCR_H 18e5a7ba87SHavard Skinnemoen 19e5a7ba87SHavard Skinnemoen #include "exec/memory.h" 20e5a7ba87SHavard Skinnemoen #include "hw/sysbus.h" 21e5a7ba87SHavard Skinnemoen 22e5a7ba87SHavard Skinnemoen /* 23c3e9e73aSHao Wu * NPCM7XX PWRON STRAP bit fields 24c3e9e73aSHao Wu * 12: SPI0 powered by VSBV3 at 1.8V 25c3e9e73aSHao Wu * 11: System flash attached to BMC 26c3e9e73aSHao Wu * 10: BSP alternative pins. 27c3e9e73aSHao Wu * 9:8: Flash UART command route enabled. 28c3e9e73aSHao Wu * 7: Security enabled. 29c3e9e73aSHao Wu * 6: HI-Z state control. 30c3e9e73aSHao Wu * 5: ECC disabled. 31c3e9e73aSHao Wu * 4: Reserved 32c3e9e73aSHao Wu * 3: JTAG2 enabled. 33c3e9e73aSHao Wu * 2:0: CPU and DRAM clock frequency. 34c3e9e73aSHao Wu */ 35c3e9e73aSHao Wu #define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12) 36c3e9e73aSHao Wu #define NPCM7XX_PWRON_STRAP_SFAB BIT(11) 37c3e9e73aSHao Wu #define NPCM7XX_PWRON_STRAP_BSPA BIT(10) 38c3e9e73aSHao Wu #define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8) 39c3e9e73aSHao Wu #define FUP_NORM_UART2 3 40c3e9e73aSHao Wu #define FUP_PROG_UART3 2 41c3e9e73aSHao Wu #define FUP_PROG_UART2 1 42c3e9e73aSHao Wu #define FUP_NORM_UART3 0 43c3e9e73aSHao Wu #define NPCM7XX_PWRON_STRAP_SECEN BIT(7) 44c3e9e73aSHao Wu #define NPCM7XX_PWRON_STRAP_HIZ BIT(6) 45c3e9e73aSHao Wu #define NPCM7XX_PWRON_STRAP_ECC BIT(5) 46c3e9e73aSHao Wu #define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4) 47c3e9e73aSHao Wu #define NPCM7XX_PWRON_STRAP_J2EN BIT(3) 48c3e9e73aSHao Wu #define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x) 49c3e9e73aSHao Wu #define CKFRQ_SKIPINIT 0x000 50c3e9e73aSHao Wu #define CKFRQ_DEFAULT 0x111 51c3e9e73aSHao Wu 52c3e9e73aSHao Wu /* 53e5a7ba87SHavard Skinnemoen * Number of registers in our device state structure. Don't change this without 54e5a7ba87SHavard Skinnemoen * incrementing the version_id in the vmstate. 55e5a7ba87SHavard Skinnemoen */ 56e5a7ba87SHavard Skinnemoen #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t)) 57e5a7ba87SHavard Skinnemoen 58c79aa350SPhilippe Mathieu-Daudé struct NPCM7xxGCRState { 59e5a7ba87SHavard Skinnemoen SysBusDevice parent; 60e5a7ba87SHavard Skinnemoen 61e5a7ba87SHavard Skinnemoen MemoryRegion iomem; 62e5a7ba87SHavard Skinnemoen 63e5a7ba87SHavard Skinnemoen uint32_t regs[NPCM7XX_GCR_NR_REGS]; 64e5a7ba87SHavard Skinnemoen 65e5a7ba87SHavard Skinnemoen uint32_t reset_pwron; 66e5a7ba87SHavard Skinnemoen uint32_t reset_mdlr; 67e5a7ba87SHavard Skinnemoen uint32_t reset_intcr3; 68c79aa350SPhilippe Mathieu-Daudé }; 69e5a7ba87SHavard Skinnemoen 70e5a7ba87SHavard Skinnemoen #define TYPE_NPCM7XX_GCR "npcm7xx-gcr" 71c79aa350SPhilippe Mathieu-Daudé OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR) 72e5a7ba87SHavard Skinnemoen 73*506af233SHao Wu #endif /* NPCM_GCR_H */ 74