1e331f79eSHavard Skinnemoen /* 2e331f79eSHavard Skinnemoen * Nuvoton NPCM7xx Clock Control Registers. 3e331f79eSHavard Skinnemoen * 4e331f79eSHavard Skinnemoen * Copyright 2020 Google LLC 5e331f79eSHavard Skinnemoen * 6e331f79eSHavard Skinnemoen * This program is free software; you can redistribute it and/or modify it 7e331f79eSHavard Skinnemoen * under the terms of the GNU General Public License as published by the 8e331f79eSHavard Skinnemoen * Free Software Foundation; either version 2 of the License, or 9e331f79eSHavard Skinnemoen * (at your option) any later version. 10e331f79eSHavard Skinnemoen * 11e331f79eSHavard Skinnemoen * This program is distributed in the hope that it will be useful, but WITHOUT 12e331f79eSHavard Skinnemoen * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13e331f79eSHavard Skinnemoen * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14e331f79eSHavard Skinnemoen * for more details. 15e331f79eSHavard Skinnemoen */ 16e331f79eSHavard Skinnemoen #ifndef NPCM7XX_CLK_H 17e331f79eSHavard Skinnemoen #define NPCM7XX_CLK_H 18e331f79eSHavard Skinnemoen 19e331f79eSHavard Skinnemoen #include "exec/memory.h" 20e331f79eSHavard Skinnemoen #include "hw/sysbus.h" 21e331f79eSHavard Skinnemoen 22e331f79eSHavard Skinnemoen /* 23e331f79eSHavard Skinnemoen * The reference clock frequency for the timer modules, and the SECCNT and 24e331f79eSHavard Skinnemoen * CNTR25M registers in this module, is always 25 MHz. 25e331f79eSHavard Skinnemoen */ 26e331f79eSHavard Skinnemoen #define NPCM7XX_TIMER_REF_HZ (25000000) 27e331f79eSHavard Skinnemoen 28e331f79eSHavard Skinnemoen /* 29e331f79eSHavard Skinnemoen * Number of registers in our device state structure. Don't change this without 30e331f79eSHavard Skinnemoen * incrementing the version_id in the vmstate. 31e331f79eSHavard Skinnemoen */ 32e331f79eSHavard Skinnemoen #define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t)) 33e331f79eSHavard Skinnemoen 347d378ed6SHao Wu #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" 357d378ed6SHao Wu 36e331f79eSHavard Skinnemoen typedef struct NPCM7xxCLKState { 37e331f79eSHavard Skinnemoen SysBusDevice parent; 38e331f79eSHavard Skinnemoen 39e331f79eSHavard Skinnemoen MemoryRegion iomem; 40e331f79eSHavard Skinnemoen 41e331f79eSHavard Skinnemoen uint32_t regs[NPCM7XX_CLK_NR_REGS]; 42e331f79eSHavard Skinnemoen 43e331f79eSHavard Skinnemoen /* Time reference for SECCNT and CNTR25M, initialized by power on reset */ 44e331f79eSHavard Skinnemoen int64_t ref_ns; 45e331f79eSHavard Skinnemoen } NPCM7xxCLKState; 46e331f79eSHavard Skinnemoen 47e331f79eSHavard Skinnemoen #define TYPE_NPCM7XX_CLK "npcm7xx-clk" 48e331f79eSHavard Skinnemoen #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK) 49e331f79eSHavard Skinnemoen 50e331f79eSHavard Skinnemoen #endif /* NPCM7XX_CLK_H */ 51