19a52d999SPeter Maydell /* 29a52d999SPeter Maydell * ARM MPS2 FPGAIO emulation 39a52d999SPeter Maydell * 49a52d999SPeter Maydell * Copyright (c) 2018 Linaro Limited 59a52d999SPeter Maydell * Written by Peter Maydell 69a52d999SPeter Maydell * 79a52d999SPeter Maydell * This program is free software; you can redistribute it and/or modify 89a52d999SPeter Maydell * it under the terms of the GNU General Public License version 2 or 99a52d999SPeter Maydell * (at your option) any later version. 109a52d999SPeter Maydell */ 119a52d999SPeter Maydell 129a52d999SPeter Maydell /* This is a model of the FPGAIO register block in the AN505 139a52d999SPeter Maydell * FPGA image for the MPS2 dev board; it is documented in the 149a52d999SPeter Maydell * application note: 159a52d999SPeter Maydell * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html 169a52d999SPeter Maydell * 179a52d999SPeter Maydell * QEMU interface: 189a52d999SPeter Maydell * + sysbus MMIO region 0: the register bank 199a52d999SPeter Maydell */ 209a52d999SPeter Maydell 219a52d999SPeter Maydell #ifndef MPS2_FPGAIO_H 229a52d999SPeter Maydell #define MPS2_FPGAIO_H 239a52d999SPeter Maydell 249a52d999SPeter Maydell #include "hw/sysbus.h" 259a52d999SPeter Maydell 269a52d999SPeter Maydell #define TYPE_MPS2_FPGAIO "mps2-fpgaio" 279a52d999SPeter Maydell #define MPS2_FPGAIO(obj) OBJECT_CHECK(MPS2FPGAIO, (obj), TYPE_MPS2_FPGAIO) 289a52d999SPeter Maydell 299a52d999SPeter Maydell typedef struct { 309a52d999SPeter Maydell /*< private >*/ 319a52d999SPeter Maydell SysBusDevice parent_obj; 329a52d999SPeter Maydell 339a52d999SPeter Maydell /*< public >*/ 349a52d999SPeter Maydell MemoryRegion iomem; 359a52d999SPeter Maydell 369a52d999SPeter Maydell uint32_t led0; 379a52d999SPeter Maydell uint32_t prescale; 389a52d999SPeter Maydell uint32_t misc; 399a52d999SPeter Maydell 409a52d999SPeter Maydell uint32_t prescale_clk; 41*a1982f90SPeter Maydell 42*a1982f90SPeter Maydell /* These hold the CLOCK_VIRTUAL ns tick when the CLK1HZ/CLK100HZ was zero */ 43*a1982f90SPeter Maydell int64_t clk1hz_tick_offset; 44*a1982f90SPeter Maydell int64_t clk100hz_tick_offset; 459a52d999SPeter Maydell } MPS2FPGAIO; 469a52d999SPeter Maydell 479a52d999SPeter Maydell #endif 48