1*1f93a6e4SLeon Alrae /* 2*1f93a6e4SLeon Alrae * Cluster Power Controller emulation 3*1f93a6e4SLeon Alrae * 4*1f93a6e4SLeon Alrae * Copyright (c) 2016 Imagination Technologies 5*1f93a6e4SLeon Alrae * 6*1f93a6e4SLeon Alrae * This library is free software; you can redistribute it and/or 7*1f93a6e4SLeon Alrae * modify it under the terms of the GNU Lesser General Public 8*1f93a6e4SLeon Alrae * License as published by the Free Software Foundation; either 9*1f93a6e4SLeon Alrae * version 2 of the License, or (at your option) any later version. 10*1f93a6e4SLeon Alrae * 11*1f93a6e4SLeon Alrae * This library is distributed in the hope that it will be useful, 12*1f93a6e4SLeon Alrae * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*1f93a6e4SLeon Alrae * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14*1f93a6e4SLeon Alrae * Lesser General Public License for more details. 15*1f93a6e4SLeon Alrae * 16*1f93a6e4SLeon Alrae * You should have received a copy of the GNU Lesser General Public 17*1f93a6e4SLeon Alrae * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18*1f93a6e4SLeon Alrae */ 19*1f93a6e4SLeon Alrae 20*1f93a6e4SLeon Alrae #ifndef MIPS_CPC_H 21*1f93a6e4SLeon Alrae #define MIPS_CPC_H 22*1f93a6e4SLeon Alrae 23*1f93a6e4SLeon Alrae #define CPC_ADDRSPACE_SZ 0x6000 24*1f93a6e4SLeon Alrae 25*1f93a6e4SLeon Alrae /* CPC blocks offsets relative to base address */ 26*1f93a6e4SLeon Alrae #define CPC_CL_BASE_OFS 0x2000 27*1f93a6e4SLeon Alrae #define CPC_CO_BASE_OFS 0x4000 28*1f93a6e4SLeon Alrae 29*1f93a6e4SLeon Alrae /* CPC register offsets relative to block offsets */ 30*1f93a6e4SLeon Alrae #define CPC_VP_STOP_OFS 0x20 31*1f93a6e4SLeon Alrae #define CPC_VP_RUN_OFS 0x28 32*1f93a6e4SLeon Alrae #define CPC_VP_RUNNING_OFS 0x30 33*1f93a6e4SLeon Alrae 34*1f93a6e4SLeon Alrae #define TYPE_MIPS_CPC "mips-cpc" 35*1f93a6e4SLeon Alrae #define MIPS_CPC(obj) OBJECT_CHECK(MIPSCPCState, (obj), TYPE_MIPS_CPC) 36*1f93a6e4SLeon Alrae 37*1f93a6e4SLeon Alrae typedef struct MIPSCPCState { 38*1f93a6e4SLeon Alrae SysBusDevice parent_obj; 39*1f93a6e4SLeon Alrae 40*1f93a6e4SLeon Alrae uint32_t num_vp; 41*1f93a6e4SLeon Alrae uint64_t vp_start_running; /* VPs running from restart */ 42*1f93a6e4SLeon Alrae 43*1f93a6e4SLeon Alrae MemoryRegion mr; 44*1f93a6e4SLeon Alrae uint64_t vp_running; /* Indicates which VPs are in the run state */ 45*1f93a6e4SLeon Alrae } MIPSCPCState; 46*1f93a6e4SLeon Alrae 47*1f93a6e4SLeon Alrae #endif /* MIPS_CPC_H */ 48