1*3400b15bSBin Meng /* 2*3400b15bSBin Meng * Microchip PolarFire SoC DDR Memory Controller module emulation 3*3400b15bSBin Meng * 4*3400b15bSBin Meng * Copyright (c) 2020 Wind River Systems, Inc. 5*3400b15bSBin Meng * 6*3400b15bSBin Meng * Author: 7*3400b15bSBin Meng * Bin Meng <bin.meng@windriver.com> 8*3400b15bSBin Meng * 9*3400b15bSBin Meng * This program is free software; you can redistribute it and/or 10*3400b15bSBin Meng * modify it under the terms of the GNU General Public License as 11*3400b15bSBin Meng * published by the Free Software Foundation; either version 2 or 12*3400b15bSBin Meng * (at your option) version 3 of the License. 13*3400b15bSBin Meng * 14*3400b15bSBin Meng * This program is distributed in the hope that it will be useful, 15*3400b15bSBin Meng * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*3400b15bSBin Meng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*3400b15bSBin Meng * GNU General Public License for more details. 18*3400b15bSBin Meng * 19*3400b15bSBin Meng * You should have received a copy of the GNU General Public License along 20*3400b15bSBin Meng * with this program; if not, see <http://www.gnu.org/licenses/>. 21*3400b15bSBin Meng */ 22*3400b15bSBin Meng 23*3400b15bSBin Meng #ifndef MCHP_PFSOC_DMC_H 24*3400b15bSBin Meng #define MCHP_PFSOC_DMC_H 25*3400b15bSBin Meng 26*3400b15bSBin Meng /* DDR SGMII PHY module */ 27*3400b15bSBin Meng 28*3400b15bSBin Meng #define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE 0x1000 29*3400b15bSBin Meng 30*3400b15bSBin Meng typedef struct MchpPfSoCDdrSgmiiPhyState { 31*3400b15bSBin Meng SysBusDevice parent; 32*3400b15bSBin Meng MemoryRegion sgmii_phy; 33*3400b15bSBin Meng } MchpPfSoCDdrSgmiiPhyState; 34*3400b15bSBin Meng 35*3400b15bSBin Meng #define TYPE_MCHP_PFSOC_DDR_SGMII_PHY "mchp.pfsoc.ddr_sgmii_phy" 36*3400b15bSBin Meng 37*3400b15bSBin Meng #define MCHP_PFSOC_DDR_SGMII_PHY(obj) \ 38*3400b15bSBin Meng OBJECT_CHECK(MchpPfSoCDdrSgmiiPhyState, (obj), \ 39*3400b15bSBin Meng TYPE_MCHP_PFSOC_DDR_SGMII_PHY) 40*3400b15bSBin Meng 41*3400b15bSBin Meng /* DDR CFG module */ 42*3400b15bSBin Meng 43*3400b15bSBin Meng #define MCHP_PFSOC_DDR_CFG_REG_SIZE 0x40000 44*3400b15bSBin Meng 45*3400b15bSBin Meng typedef struct MchpPfSoCDdrCfgState { 46*3400b15bSBin Meng SysBusDevice parent; 47*3400b15bSBin Meng MemoryRegion cfg; 48*3400b15bSBin Meng } MchpPfSoCDdrCfgState; 49*3400b15bSBin Meng 50*3400b15bSBin Meng #define TYPE_MCHP_PFSOC_DDR_CFG "mchp.pfsoc.ddr_cfg" 51*3400b15bSBin Meng 52*3400b15bSBin Meng #define MCHP_PFSOC_DDR_CFG(obj) \ 53*3400b15bSBin Meng OBJECT_CHECK(MchpPfSoCDdrCfgState, (obj), \ 54*3400b15bSBin Meng TYPE_MCHP_PFSOC_DDR_CFG) 55*3400b15bSBin Meng 56*3400b15bSBin Meng #endif /* MCHP_PFSOC_DMC_H */ 57