13400b15bSBin Meng /* 23400b15bSBin Meng * Microchip PolarFire SoC DDR Memory Controller module emulation 33400b15bSBin Meng * 43400b15bSBin Meng * Copyright (c) 2020 Wind River Systems, Inc. 53400b15bSBin Meng * 63400b15bSBin Meng * Author: 73400b15bSBin Meng * Bin Meng <bin.meng@windriver.com> 83400b15bSBin Meng * 93400b15bSBin Meng * This program is free software; you can redistribute it and/or 103400b15bSBin Meng * modify it under the terms of the GNU General Public License as 113400b15bSBin Meng * published by the Free Software Foundation; either version 2 or 123400b15bSBin Meng * (at your option) version 3 of the License. 133400b15bSBin Meng * 143400b15bSBin Meng * This program is distributed in the hope that it will be useful, 153400b15bSBin Meng * but WITHOUT ANY WARRANTY; without even the implied warranty of 163400b15bSBin Meng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 173400b15bSBin Meng * GNU General Public License for more details. 183400b15bSBin Meng * 193400b15bSBin Meng * You should have received a copy of the GNU General Public License along 203400b15bSBin Meng * with this program; if not, see <http://www.gnu.org/licenses/>. 213400b15bSBin Meng */ 223400b15bSBin Meng 233400b15bSBin Meng #ifndef MCHP_PFSOC_DMC_H 243400b15bSBin Meng #define MCHP_PFSOC_DMC_H 253400b15bSBin Meng 26*7a5951f6SMarkus Armbruster #include "hw/sysbus.h" 27*7a5951f6SMarkus Armbruster 283400b15bSBin Meng /* DDR SGMII PHY module */ 293400b15bSBin Meng 303400b15bSBin Meng #define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE 0x1000 313400b15bSBin Meng 323400b15bSBin Meng typedef struct MchpPfSoCDdrSgmiiPhyState { 333400b15bSBin Meng SysBusDevice parent; 343400b15bSBin Meng MemoryRegion sgmii_phy; 353400b15bSBin Meng } MchpPfSoCDdrSgmiiPhyState; 363400b15bSBin Meng 373400b15bSBin Meng #define TYPE_MCHP_PFSOC_DDR_SGMII_PHY "mchp.pfsoc.ddr_sgmii_phy" 383400b15bSBin Meng 393400b15bSBin Meng #define MCHP_PFSOC_DDR_SGMII_PHY(obj) \ 403400b15bSBin Meng OBJECT_CHECK(MchpPfSoCDdrSgmiiPhyState, (obj), \ 413400b15bSBin Meng TYPE_MCHP_PFSOC_DDR_SGMII_PHY) 423400b15bSBin Meng 433400b15bSBin Meng /* DDR CFG module */ 443400b15bSBin Meng 453400b15bSBin Meng #define MCHP_PFSOC_DDR_CFG_REG_SIZE 0x40000 463400b15bSBin Meng 473400b15bSBin Meng typedef struct MchpPfSoCDdrCfgState { 483400b15bSBin Meng SysBusDevice parent; 493400b15bSBin Meng MemoryRegion cfg; 503400b15bSBin Meng } MchpPfSoCDdrCfgState; 513400b15bSBin Meng 523400b15bSBin Meng #define TYPE_MCHP_PFSOC_DDR_CFG "mchp.pfsoc.ddr_cfg" 533400b15bSBin Meng 543400b15bSBin Meng #define MCHP_PFSOC_DDR_CFG(obj) \ 553400b15bSBin Meng OBJECT_CHECK(MchpPfSoCDdrCfgState, (obj), \ 563400b15bSBin Meng TYPE_MCHP_PFSOC_DDR_CFG) 573400b15bSBin Meng 583400b15bSBin Meng #endif /* MCHP_PFSOC_DMC_H */ 59