1b514f432SMark Cave-Ayland /* 2b514f432SMark Cave-Ayland * HP-PARISC Lasi chipset emulation. 3b514f432SMark Cave-Ayland * 4b514f432SMark Cave-Ayland * (C) 2019 by Helge Deller <deller@gmx.de> 5b514f432SMark Cave-Ayland * 6b514f432SMark Cave-Ayland * This work is licensed under the GNU GPL license version 2 or later. 7b514f432SMark Cave-Ayland * 8b514f432SMark Cave-Ayland * Documentation available at: 9b514f432SMark Cave-Ayland * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf 10b514f432SMark Cave-Ayland */ 11b514f432SMark Cave-Ayland 12b514f432SMark Cave-Ayland #ifndef LASI_H 13b514f432SMark Cave-Ayland #define LASI_H 14b514f432SMark Cave-Ayland 15b514f432SMark Cave-Ayland #define TYPE_LASI_CHIP "lasi-chip" 16b514f432SMark Cave-Ayland OBJECT_DECLARE_SIMPLE_TYPE(LasiState, LASI_CHIP) 17b514f432SMark Cave-Ayland 18b514f432SMark Cave-Ayland #define LASI_IRR 0x00 /* RO */ 19b514f432SMark Cave-Ayland #define LASI_IMR 0x04 20b514f432SMark Cave-Ayland #define LASI_IPR 0x08 21b514f432SMark Cave-Ayland #define LASI_ICR 0x0c 22b514f432SMark Cave-Ayland #define LASI_IAR 0x10 23b514f432SMark Cave-Ayland 24b514f432SMark Cave-Ayland #define LASI_PCR 0x0C000 /* LASI Power Control register */ 25b514f432SMark Cave-Ayland #define LASI_ERRLOG 0x0C004 /* LASI Error Logging register */ 26b514f432SMark Cave-Ayland #define LASI_VER 0x0C008 /* LASI Version Control register */ 27b514f432SMark Cave-Ayland #define LASI_IORESET 0x0C00C /* LASI I/O Reset register */ 28b514f432SMark Cave-Ayland #define LASI_AMR 0x0C010 /* LASI Arbitration Mask register */ 29b514f432SMark Cave-Ayland #define LASI_IO_CONF 0x7FFFE /* LASI primary configuration register */ 30b514f432SMark Cave-Ayland #define LASI_IO_CONF2 0x7FFFF /* LASI secondary configuration register */ 31b514f432SMark Cave-Ayland 32b514f432SMark Cave-Ayland #define LASI_BIT(x) (1ul << (x)) 33b514f432SMark Cave-Ayland #define LASI_IRQ_BITS (LASI_BIT(5) | LASI_BIT(7) | LASI_BIT(8) | LASI_BIT(9) \ 34b514f432SMark Cave-Ayland | LASI_BIT(13) | LASI_BIT(14) | LASI_BIT(16) | LASI_BIT(17) \ 35b514f432SMark Cave-Ayland | LASI_BIT(18) | LASI_BIT(19) | LASI_BIT(20) | LASI_BIT(21) \ 36b514f432SMark Cave-Ayland | LASI_BIT(26)) 37b514f432SMark Cave-Ayland 38b514f432SMark Cave-Ayland #define ICR_BUS_ERROR_BIT LASI_BIT(8) /* bit 8 in ICR */ 39b514f432SMark Cave-Ayland #define ICR_TOC_BIT LASI_BIT(1) /* bit 1 in ICR */ 40b514f432SMark Cave-Ayland 41*cb9f6c4bSMark Cave-Ayland #define LASI_IRQS 27 42*cb9f6c4bSMark Cave-Ayland 430f04d577SMark Cave-Ayland #define LASI_IRQ_HPA 14 440f04d577SMark Cave-Ayland #define LASI_IRQ_UART_HPA 5 450f04d577SMark Cave-Ayland #define LASI_IRQ_LPT_HPA 7 460f04d577SMark Cave-Ayland #define LASI_IRQ_LAN_HPA 8 470f04d577SMark Cave-Ayland #define LASI_IRQ_SCSI_HPA 9 480f04d577SMark Cave-Ayland #define LASI_IRQ_AUDIO_HPA 13 490f04d577SMark Cave-Ayland #define LASI_IRQ_PS2KBD_HPA 26 500f04d577SMark Cave-Ayland #define LASI_IRQ_PS2MOU_HPA 26 510f04d577SMark Cave-Ayland 52b514f432SMark Cave-Ayland struct LasiState { 53b514f432SMark Cave-Ayland PCIHostState parent_obj; 54b514f432SMark Cave-Ayland 55b514f432SMark Cave-Ayland uint32_t irr; 56b514f432SMark Cave-Ayland uint32_t imr; 57b514f432SMark Cave-Ayland uint32_t ipr; 58b514f432SMark Cave-Ayland uint32_t icr; 59b514f432SMark Cave-Ayland uint32_t iar; 60b514f432SMark Cave-Ayland 61b514f432SMark Cave-Ayland uint32_t errlog; 62b514f432SMark Cave-Ayland uint32_t amr; 63b514f432SMark Cave-Ayland uint32_t rtc; 64b514f432SMark Cave-Ayland time_t rtc_ref; 65b514f432SMark Cave-Ayland 66b514f432SMark Cave-Ayland MemoryRegion this_mem; 67b514f432SMark Cave-Ayland }; 68b514f432SMark Cave-Ayland 69b514f432SMark Cave-Ayland #endif 70