1 /* 2 * ARM IoT Kit security controller 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the security controller which is part of the 13 * Arm IoT Kit and documented in 14 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 15 * 16 * QEMU interface: 17 * + sysbus MMIO region 0 is the "secure privilege control block" registers 18 * + sysbus MMIO region 1 is the "non-secure privilege control block" registers 19 * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses 20 * should RAZ/WI or bus error 21 * Controlling the 2 APB PPCs in the IoTKit: 22 * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec 23 * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap 24 * + named GPIO outputs apb_ppc{0,1}_irq_enable 25 * + named GPIO outputs apb_ppc{0,1}_irq_clear 26 * + named GPIO inputs apb_ppc{0,1}_irq_status 27 * Controlling each of the 4 expansion APB PPCs which a system using the IoTKit 28 * might provide: 29 * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] 30 * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] 31 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable 32 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear 33 * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status 34 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit 35 * might provide: 36 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] 37 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] 38 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable 39 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear 40 * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status 41 */ 42 43 #ifndef IOTKIT_SECCTL_H 44 #define IOTKIT_SECCTL_H 45 46 #include "hw/sysbus.h" 47 48 #define TYPE_IOTKIT_SECCTL "iotkit-secctl" 49 #define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL) 50 51 #define IOTS_APB_PPC0_NUM_PORTS 3 52 #define IOTS_APB_PPC1_NUM_PORTS 1 53 #define IOTS_PPC_NUM_PORTS 16 54 #define IOTS_NUM_APB_PPC 2 55 #define IOTS_NUM_APB_EXP_PPC 4 56 #define IOTS_NUM_AHB_EXP_PPC 4 57 58 typedef struct IoTKitSecCtl IoTKitSecCtl; 59 60 /* State and IRQ lines relating to a PPC. For the 61 * PPCs in the IoTKit not all the IRQ lines are used. 62 */ 63 typedef struct IoTKitSecCtlPPC { 64 qemu_irq nonsec[IOTS_PPC_NUM_PORTS]; 65 qemu_irq ap[IOTS_PPC_NUM_PORTS]; 66 qemu_irq irq_enable; 67 qemu_irq irq_clear; 68 69 uint32_t ns; 70 uint32_t sp; 71 uint32_t nsp; 72 73 /* Number of ports actually present */ 74 int numports; 75 /* Offset of this PPC's interrupt bits in SECPPCINTSTAT */ 76 int irq_bit_offset; 77 IoTKitSecCtl *parent; 78 } IoTKitSecCtlPPC; 79 80 struct IoTKitSecCtl { 81 /*< private >*/ 82 SysBusDevice parent_obj; 83 84 /*< public >*/ 85 qemu_irq sec_resp_cfg; 86 87 MemoryRegion s_regs; 88 MemoryRegion ns_regs; 89 90 uint32_t secppcintstat; 91 uint32_t secppcinten; 92 uint32_t secrespcfg; 93 94 IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; 95 IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; 96 IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC]; 97 }; 98 99 #endif 100