10a7bc1c0SAndrey Smirnov /* 20a7bc1c0SAndrey Smirnov * Copyright (c) 2017, Impinj, Inc. 30a7bc1c0SAndrey Smirnov * 40a7bc1c0SAndrey Smirnov * i.MX7 SNVS block emulation code 50a7bc1c0SAndrey Smirnov * 60a7bc1c0SAndrey Smirnov * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 70a7bc1c0SAndrey Smirnov * 80a7bc1c0SAndrey Smirnov * This work is licensed under the terms of the GNU GPL, version 2 or later. 90a7bc1c0SAndrey Smirnov * See the COPYING file in the top-level directory. 100a7bc1c0SAndrey Smirnov */ 110a7bc1c0SAndrey Smirnov 120a7bc1c0SAndrey Smirnov #ifndef IMX7_SNVS_H 130a7bc1c0SAndrey Smirnov #define IMX7_SNVS_H 140a7bc1c0SAndrey Smirnov 150a7bc1c0SAndrey Smirnov #include "qemu/bitops.h" 160a7bc1c0SAndrey Smirnov #include "hw/sysbus.h" 17db1015e9SEduardo Habkost #include "qom/object.h" 180a7bc1c0SAndrey Smirnov 190a7bc1c0SAndrey Smirnov 200a7bc1c0SAndrey Smirnov enum IMX7SNVSRegisters { 210a7bc1c0SAndrey Smirnov SNVS_LPCR = 0x38, 220a7bc1c0SAndrey Smirnov SNVS_LPCR_TOP = BIT(6), 23*6f9c3aaaSNikita Ostrenkov SNVS_LPCR_DP_EN = BIT(5), 24*6f9c3aaaSNikita Ostrenkov SNVS_LPSRTCMR = 0x050, /* Secure Real Time Counter MSB Register */ 25*6f9c3aaaSNikita Ostrenkov SNVS_LPSRTCLR = 0x054, /* Secure Real Time Counter LSB Register */ 260a7bc1c0SAndrey Smirnov }; 270a7bc1c0SAndrey Smirnov 280a7bc1c0SAndrey Smirnov #define TYPE_IMX7_SNVS "imx7.snvs" 298063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(IMX7SNVSState, IMX7_SNVS) 300a7bc1c0SAndrey Smirnov 31db1015e9SEduardo Habkost struct IMX7SNVSState { 320a7bc1c0SAndrey Smirnov /* <private> */ 330a7bc1c0SAndrey Smirnov SysBusDevice parent_obj; 340a7bc1c0SAndrey Smirnov 350a7bc1c0SAndrey Smirnov MemoryRegion mmio; 36*6f9c3aaaSNikita Ostrenkov 37*6f9c3aaaSNikita Ostrenkov uint64_t tick_offset; 38*6f9c3aaaSNikita Ostrenkov uint64_t lpcr; 39db1015e9SEduardo Habkost }; 400a7bc1c0SAndrey Smirnov 410a7bc1c0SAndrey Smirnov #endif /* IMX7_SNVS_H */ 42