1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 #ifndef ASPEED_SCU_H 12 #define ASPEED_SCU_H 13 14 #include "hw/sysbus.h" 15 16 #define TYPE_ASPEED_SCU "aspeed.scu" 17 #define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU) 18 19 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) 20 21 typedef struct AspeedSCUState { 22 /*< private >*/ 23 SysBusDevice parent_obj; 24 25 /*< public >*/ 26 MemoryRegion iomem; 27 28 uint32_t regs[ASPEED_SCU_NR_REGS]; 29 uint32_t silicon_rev; 30 uint32_t hw_strap1; 31 uint32_t hw_strap2; 32 } AspeedSCUState; 33 34 #define AST2400_A0_SILICON_REV 0x02000303U 35 #define AST2500_A0_SILICON_REV 0x04000303U 36 37 extern bool is_supported_silicon_rev(uint32_t silicon_rev); 38 39 /* 40 * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions 41 * were added. 42 * 43 * Original header file : 44 * arch/arm/mach-aspeed/include/mach/regs-scu.h 45 * 46 * Copyright (C) 2012-2020 ASPEED Technology Inc. 47 * 48 * This program is free software; you can redistribute it and/or modify 49 * it under the terms of the GNU General Public License version 2 as 50 * published by the Free Software Foundation. 51 * 52 * History : 53 * 1. 2012/12/29 Ryan Chen Create 54 */ 55 56 /* Hardware Strapping Register definition (for Aspeed AST2400 SOC) 57 * 58 * 31:29 Software defined strapping registers 59 * 28:27 DRAM size setting (for VGA driver use) 60 * 26:24 DRAM configuration setting 61 * 23 Enable 25 MHz reference clock input 62 * 22 Enable GPIOE pass-through mode 63 * 21 Enable GPIOD pass-through mode 64 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 65 * 19 Disable ACPI function 66 * 23,18 Clock source selection 67 * 17 Enable BMC 2nd boot watchdog timer 68 * 16 SuperIO configuration address selection 69 * 15 VGA Class Code selection 70 * 14 Enable LPC dedicated reset pin function 71 * 13:12 SPI mode selection 72 * 11:10 CPU/AHB clock frequency ratio selection 73 * 9:8 H-PLL default clock frequency selection 74 * 7 Define MAC#2 interface 75 * 6 Define MAC#1 interface 76 * 5 Enable VGA BIOS ROM 77 * 4 Boot flash memory extended option 78 * 3:2 VGA memory size selection 79 * 1:0 BMC CPU boot code selection 80 */ 81 #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) 82 #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) 83 84 #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) 85 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) 86 #define DRAM_SIZE_64MB 0 87 #define DRAM_SIZE_128MB 1 88 #define DRAM_SIZE_256MB 2 89 #define DRAM_SIZE_512MB 3 90 91 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) 92 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) 93 94 #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) 95 #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) 96 #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) 97 #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) 98 99 /* bit 23, 18 [1,0] */ 100 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ 101 | (((x) & 0x1) << 18)) 102 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ 103 | (((x) >> 18) & 0x1)) 104 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) 105 #define AST2400_CLK_25M_IN (0x1 << 23) 106 #define AST2400_CLK_24M_IN 0 107 #define AST2400_CLK_48M_IN 1 108 #define AST2400_CLK_25M_IN_24M_USB_CKI 2 109 #define AST2400_CLK_25M_IN_48M_USB_CKI 3 110 111 #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) 112 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) 113 #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) 114 #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) 115 116 #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) 117 #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) 118 #define SCU_HW_STRAP_SPI_DIS 0 119 #define SCU_HW_STRAP_SPI_MASTER 1 120 #define SCU_HW_STRAP_SPI_M_S_EN 2 121 #define SCU_HW_STRAP_SPI_PASS_THROUGH 3 122 123 #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) 124 #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) 125 #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) 126 #define AST2400_CPU_AHB_RATIO_1_1 0 127 #define AST2400_CPU_AHB_RATIO_2_1 1 128 #define AST2400_CPU_AHB_RATIO_4_1 2 129 #define AST2400_CPU_AHB_RATIO_3_1 3 130 131 #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) 132 #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) 133 #define AST2400_CPU_384MHZ 0 134 #define AST2400_CPU_360MHZ 1 135 #define AST2400_CPU_336MHZ 2 136 #define AST2400_CPU_408MHZ 3 137 138 #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) 139 #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) 140 #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) 141 #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) 142 143 #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) 144 #define SCU_HW_STRAP_VGA_MASK (0x3 << 2) 145 #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) 146 #define VGA_8M_DRAM 0 147 #define VGA_16M_DRAM 1 148 #define VGA_32M_DRAM 2 149 #define VGA_64M_DRAM 3 150 151 #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) 152 #define AST2400_NOR_BOOT 0 153 #define AST2400_NAND_BOOT 1 154 #define AST2400_SPI_BOOT 2 155 #define AST2400_DIS_BOOT 3 156 157 #endif /* ASPEED_SCU_H */ 158