1*c5475b3fSJoel Stanley /* 2*c5475b3fSJoel Stanley * ASPEED Hash and Crypto Engine 3*c5475b3fSJoel Stanley * 4*c5475b3fSJoel Stanley * Copyright (C) 2021 IBM Corp. 5*c5475b3fSJoel Stanley * 6*c5475b3fSJoel Stanley * SPDX-License-Identifier: GPL-2.0-or-later 7*c5475b3fSJoel Stanley */ 8*c5475b3fSJoel Stanley 9*c5475b3fSJoel Stanley #ifndef ASPEED_HACE_H 10*c5475b3fSJoel Stanley #define ASPEED_HACE_H 11*c5475b3fSJoel Stanley 12*c5475b3fSJoel Stanley #include "hw/sysbus.h" 13*c5475b3fSJoel Stanley 14*c5475b3fSJoel Stanley #define TYPE_ASPEED_HACE "aspeed.hace" 15*c5475b3fSJoel Stanley #define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400" 16*c5475b3fSJoel Stanley #define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500" 17*c5475b3fSJoel Stanley #define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600" 18*c5475b3fSJoel Stanley OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE) 19*c5475b3fSJoel Stanley 20*c5475b3fSJoel Stanley #define ASPEED_HACE_NR_REGS (0x64 >> 2) 21*c5475b3fSJoel Stanley 22*c5475b3fSJoel Stanley struct AspeedHACEState { 23*c5475b3fSJoel Stanley SysBusDevice parent; 24*c5475b3fSJoel Stanley 25*c5475b3fSJoel Stanley MemoryRegion iomem; 26*c5475b3fSJoel Stanley qemu_irq irq; 27*c5475b3fSJoel Stanley 28*c5475b3fSJoel Stanley uint32_t regs[ASPEED_HACE_NR_REGS]; 29*c5475b3fSJoel Stanley 30*c5475b3fSJoel Stanley MemoryRegion *dram_mr; 31*c5475b3fSJoel Stanley AddressSpace dram_as; 32*c5475b3fSJoel Stanley }; 33*c5475b3fSJoel Stanley 34*c5475b3fSJoel Stanley 35*c5475b3fSJoel Stanley struct AspeedHACEClass { 36*c5475b3fSJoel Stanley SysBusDeviceClass parent_class; 37*c5475b3fSJoel Stanley 38*c5475b3fSJoel Stanley uint32_t src_mask; 39*c5475b3fSJoel Stanley uint32_t dest_mask; 40*c5475b3fSJoel Stanley uint32_t hash_mask; 41*c5475b3fSJoel Stanley }; 42*c5475b3fSJoel Stanley 43*c5475b3fSJoel Stanley #endif /* _ASPEED_HACE_H_ */ 44