xref: /qemu/include/hw/mips/mips.h (revision c227f0995e1722a1abccc28cadf0664266bd8043)
187ecb68bSpbrook #ifndef HW_MIPS_H
287ecb68bSpbrook #define HW_MIPS_H
387ecb68bSpbrook /* Definitions for mips board emulation.  */
487ecb68bSpbrook 
587ecb68bSpbrook /* gt64xxx.c */
687ecb68bSpbrook PCIBus *pci_gt64120_init(qemu_irq *pic);
787ecb68bSpbrook 
887ecb68bSpbrook /* ds1225y.c */
9*c227f099SAnthony Liguori void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1002cb1585Saurel32 void ds1225y_set_protection(void *opaque, int protection);
1187ecb68bSpbrook 
124ce7ff6eSaurel32 /* g364fb.c */
13*c227f099SAnthony Liguori int g364fb_mm_init(target_phys_addr_t vram_base,
14*c227f099SAnthony Liguori                    target_phys_addr_t ctrl_base, int it_shift,
150add30cfSaurel32                    qemu_irq irq);
164ce7ff6eSaurel32 
1787ecb68bSpbrook /* mipsnet.c */
1887ecb68bSpbrook void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
1987ecb68bSpbrook 
2087ecb68bSpbrook /* jazz_led.c */
21*c227f099SAnthony Liguori extern void jazz_led_init(target_phys_addr_t base);
2287ecb68bSpbrook 
2387ecb68bSpbrook /* mips_int.c */
2487ecb68bSpbrook extern void cpu_mips_irq_init_cpu(CPUState *env);
2587ecb68bSpbrook 
2687ecb68bSpbrook /* mips_timer.c */
2787ecb68bSpbrook extern void cpu_mips_clock_init(CPUState *);
2887ecb68bSpbrook 
294ce7ff6eSaurel32 /* rc4030.c */
30c6945b15Saurel32 typedef struct rc4030DMAState *rc4030_dma;
31*c227f099SAnthony Liguori void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
3268238a9eSaurel32 void rc4030_dma_read(void *dma, uint8_t *buf, int len);
3368238a9eSaurel32 void rc4030_dma_write(void *dma, uint8_t *buf, int len);
3468238a9eSaurel32 
3568238a9eSaurel32 void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
3668238a9eSaurel32                   qemu_irq **irqs, rc4030_dma **dmas);
374ce7ff6eSaurel32 
38a65f56eeSaurel32 /* dp8393x.c */
39*c227f099SAnthony Liguori void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
40a65f56eeSaurel32                   qemu_irq irq, void* mem_opaque,
41*c227f099SAnthony Liguori                   void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write));
42a65f56eeSaurel32 
4387ecb68bSpbrook #endif
44