1e3355a0cSThomas Huth 2e3355a0cSThomas Huth #ifndef NEXT_CUBE_H 3e3355a0cSThomas Huth #define NEXT_CUBE_H 4e3355a0cSThomas Huth 5e3355a0cSThomas Huth #define TYPE_NEXTFB "next-fb" 6e3355a0cSThomas Huth 7c8e8bc85SThomas Huth #define TYPE_NEXTKBD "next-kbd" 8c8e8bc85SThomas Huth 9*956a7811SThomas Huth enum next_dma_chan { 10*956a7811SThomas Huth NEXTDMA_FD, 11*956a7811SThomas Huth NEXTDMA_ENRX, 12*956a7811SThomas Huth NEXTDMA_ENTX, 13*956a7811SThomas Huth NEXTDMA_SCSI, 14*956a7811SThomas Huth NEXTDMA_SCC, 15*956a7811SThomas Huth NEXTDMA_SND 16*956a7811SThomas Huth }; 17*956a7811SThomas Huth 18*956a7811SThomas Huth #define DMA_ENABLE 0x01000000 19*956a7811SThomas Huth #define DMA_SUPDATE 0x02000000 20*956a7811SThomas Huth #define DMA_COMPLETE 0x08000000 21*956a7811SThomas Huth 22*956a7811SThomas Huth #define DMA_M2DEV 0x0 23*956a7811SThomas Huth #define DMA_SETENABLE 0x00010000 24*956a7811SThomas Huth #define DMA_SETSUPDATE 0x00020000 25*956a7811SThomas Huth #define DMA_DEV2M 0x00040000 26*956a7811SThomas Huth #define DMA_CLRCOMPLETE 0x00080000 27*956a7811SThomas Huth #define DMA_RESET 0x00100000 28*956a7811SThomas Huth 29*956a7811SThomas Huth enum next_irqs { 30*956a7811SThomas Huth NEXT_FD_I, 31*956a7811SThomas Huth NEXT_KBD_I, 32*956a7811SThomas Huth NEXT_PWR_I, 33*956a7811SThomas Huth NEXT_ENRX_I, 34*956a7811SThomas Huth NEXT_ENTX_I, 35*956a7811SThomas Huth NEXT_SCSI_I, 36*956a7811SThomas Huth NEXT_CLK_I, 37*956a7811SThomas Huth NEXT_SCC_I, 38*956a7811SThomas Huth NEXT_ENTX_DMA_I, 39*956a7811SThomas Huth NEXT_ENRX_DMA_I, 40*956a7811SThomas Huth NEXT_SCSI_DMA_I, 41*956a7811SThomas Huth NEXT_SCC_DMA_I, 42*956a7811SThomas Huth NEXT_SND_I 43*956a7811SThomas Huth }; 44*956a7811SThomas Huth 45*956a7811SThomas Huth void next_irq(void *opaque, int number, int level); 46*956a7811SThomas Huth 47e3355a0cSThomas Huth #endif /* NEXT_CUBE_H */ 48