1 /* 2 * SiFive PLIC (Platform Level Interrupt Controller) interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This provides a RISC-V PLIC device 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef HW_SIFIVE_PLIC_H 22 #define HW_SIFIVE_PLIC_H 23 24 #include "hw/sysbus.h" 25 26 #define TYPE_SIFIVE_PLIC "riscv.sifive.plic" 27 28 #define SIFIVE_PLIC(obj) \ 29 OBJECT_CHECK(SiFivePLICState, (obj), TYPE_SIFIVE_PLIC) 30 31 typedef enum PLICMode { 32 PLICMode_U, 33 PLICMode_S, 34 PLICMode_H, 35 PLICMode_M 36 } PLICMode; 37 38 typedef struct PLICAddr { 39 uint32_t addrid; 40 uint32_t hartid; 41 PLICMode mode; 42 } PLICAddr; 43 44 typedef struct SiFivePLICState { 45 /*< private >*/ 46 SysBusDevice parent_obj; 47 48 /*< public >*/ 49 MemoryRegion mmio; 50 uint32_t num_addrs; 51 uint32_t num_harts; 52 uint32_t bitfield_words; 53 PLICAddr *addr_config; 54 uint32_t *source_priority; 55 uint32_t *target_priority; 56 uint32_t *pending; 57 uint32_t *claimed; 58 uint32_t *enable; 59 60 /* config */ 61 char *hart_config; 62 uint32_t hartid_base; 63 uint32_t num_sources; 64 uint32_t num_priorities; 65 uint32_t priority_base; 66 uint32_t pending_base; 67 uint32_t enable_base; 68 uint32_t enable_stride; 69 uint32_t context_base; 70 uint32_t context_stride; 71 uint32_t aperture_size; 72 } SiFivePLICState; 73 74 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, 75 uint32_t hartid_base, uint32_t num_sources, 76 uint32_t num_priorities, uint32_t priority_base, 77 uint32_t pending_base, uint32_t enable_base, 78 uint32_t enable_stride, uint32_t context_base, 79 uint32_t context_stride, uint32_t aperture_size); 80 81 #endif 82