xref: /qemu/include/hw/intc/riscv_aclint.h (revision cc63a18282d8e8cd96d8bf26c29cad2e879ff9f6)
1 /*
2  * SiFive CLINT (Core Local Interruptor) interface
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef HW_SIFIVE_CLINT_H
21 #define HW_SIFIVE_CLINT_H
22 
23 #include "hw/sysbus.h"
24 
25 #define TYPE_SIFIVE_CLINT "riscv.sifive.clint"
26 
27 #define SIFIVE_CLINT(obj) \
28     OBJECT_CHECK(SiFiveCLINTState, (obj), TYPE_SIFIVE_CLINT)
29 
30 typedef struct SiFiveCLINTState {
31     /*< private >*/
32     SysBusDevice parent_obj;
33 
34     /*< public >*/
35     MemoryRegion mmio;
36     uint32_t hartid_base;
37     uint32_t num_harts;
38     uint32_t sip_base;
39     uint32_t timecmp_base;
40     uint32_t time_base;
41     uint32_t aperture_size;
42     uint32_t timebase_freq;
43     qemu_irq *timer_irqs;
44     qemu_irq *soft_irqs;
45 } SiFiveCLINTState;
46 
47 DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
48     uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
49     uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
50     bool provide_rdtime);
51 
52 enum {
53     SIFIVE_SIP_BASE     = 0x0,
54     SIFIVE_TIMECMP_BASE = 0x4000,
55     SIFIVE_TIME_BASE    = 0xBFF8
56 };
57 
58 enum {
59     SIFIVE_CLINT_TIMEBASE_FREQ = 10000000
60 };
61 
62 #endif
63