xref: /qemu/include/hw/intc/ppc-uic.h (revision 34d0831f38fd8ca253fc77d66f54976e440f0131)
1*34d0831fSPeter Maydell /*
2*34d0831fSPeter Maydell  * "Universal" Interrupt Controller for PowerPPC 4xx embedded processors
3*34d0831fSPeter Maydell  *
4*34d0831fSPeter Maydell  * Copyright (c) 2007 Jocelyn Mayer
5*34d0831fSPeter Maydell  *
6*34d0831fSPeter Maydell  * Permission is hereby granted, free of charge, to any person obtaining a copy
7*34d0831fSPeter Maydell  * of this software and associated documentation files (the "Software"), to deal
8*34d0831fSPeter Maydell  * in the Software without restriction, including without limitation the rights
9*34d0831fSPeter Maydell  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10*34d0831fSPeter Maydell  * copies of the Software, and to permit persons to whom the Software is
11*34d0831fSPeter Maydell  * furnished to do so, subject to the following conditions:
12*34d0831fSPeter Maydell  *
13*34d0831fSPeter Maydell  * The above copyright notice and this permission notice shall be included in
14*34d0831fSPeter Maydell  * all copies or substantial portions of the Software.
15*34d0831fSPeter Maydell  *
16*34d0831fSPeter Maydell  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17*34d0831fSPeter Maydell  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18*34d0831fSPeter Maydell  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19*34d0831fSPeter Maydell  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20*34d0831fSPeter Maydell  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21*34d0831fSPeter Maydell  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22*34d0831fSPeter Maydell  * THE SOFTWARE.
23*34d0831fSPeter Maydell  */
24*34d0831fSPeter Maydell 
25*34d0831fSPeter Maydell #ifndef HW_INTC_PPC_UIC_H
26*34d0831fSPeter Maydell #define HW_INTC_PPC_UIC_H
27*34d0831fSPeter Maydell 
28*34d0831fSPeter Maydell #include "hw/sysbus.h"
29*34d0831fSPeter Maydell #include "qom/object.h"
30*34d0831fSPeter Maydell 
31*34d0831fSPeter Maydell #define TYPE_PPC_UIC "ppc-uic"
32*34d0831fSPeter Maydell OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC)
33*34d0831fSPeter Maydell 
34*34d0831fSPeter Maydell /*
35*34d0831fSPeter Maydell  * QEMU interface:
36*34d0831fSPeter Maydell  * QOM property "cpu": link to the PPC CPU
37*34d0831fSPeter Maydell  *    (no default, must be set)
38*34d0831fSPeter Maydell  * QOM property "dcr-base": base of the bank of DCR registers for the UIC
39*34d0831fSPeter Maydell  *    (default 0x30)
40*34d0831fSPeter Maydell  * QOM property "use-vectors": true if the UIC has vector registers
41*34d0831fSPeter Maydell  *    (default true)
42*34d0831fSPeter Maydell  * unnamed GPIO inputs 0..UIC_MAX_IRQ: input IRQ lines
43*34d0831fSPeter Maydell  * sysbus IRQs:
44*34d0831fSPeter Maydell  *  0 (PPCUIC_OUTPUT_INT): output INT line to the CPU
45*34d0831fSPeter Maydell  *  1 (PPCUIC_OUTPUT_CINT): output CINT line to the CPU
46*34d0831fSPeter Maydell  */
47*34d0831fSPeter Maydell 
48*34d0831fSPeter Maydell #define UIC_MAX_IRQ 32
49*34d0831fSPeter Maydell 
50*34d0831fSPeter Maydell struct PPCUIC {
51*34d0831fSPeter Maydell     /*< private >*/
52*34d0831fSPeter Maydell     SysBusDevice parent_obj;
53*34d0831fSPeter Maydell 
54*34d0831fSPeter Maydell     /*< public >*/
55*34d0831fSPeter Maydell     qemu_irq output_int;
56*34d0831fSPeter Maydell     qemu_irq output_cint;
57*34d0831fSPeter Maydell 
58*34d0831fSPeter Maydell     /* properties */
59*34d0831fSPeter Maydell     CPUState *cpu;
60*34d0831fSPeter Maydell     uint32_t dcr_base;
61*34d0831fSPeter Maydell     bool use_vectors;
62*34d0831fSPeter Maydell 
63*34d0831fSPeter Maydell     uint32_t level;  /* Remembers the state of level-triggered interrupts. */
64*34d0831fSPeter Maydell     uint32_t uicsr;  /* Status register */
65*34d0831fSPeter Maydell     uint32_t uicer;  /* Enable register */
66*34d0831fSPeter Maydell     uint32_t uiccr;  /* Critical register */
67*34d0831fSPeter Maydell     uint32_t uicpr;  /* Polarity register */
68*34d0831fSPeter Maydell     uint32_t uictr;  /* Triggering register */
69*34d0831fSPeter Maydell     uint32_t uicvcr; /* Vector configuration register */
70*34d0831fSPeter Maydell     uint32_t uicvr;
71*34d0831fSPeter Maydell };
72*34d0831fSPeter Maydell 
73*34d0831fSPeter Maydell #endif
74