17e555781SBibo Mao /* SPDX-License-Identifier: GPL-2.0-or-later */ 27e555781SBibo Mao /* 37e555781SBibo Mao * Loongson ipi interrupt header files 47e555781SBibo Mao * 57e555781SBibo Mao * Copyright (C) 2021 Loongson Technology Corporation Limited 67e555781SBibo Mao */ 77e555781SBibo Mao 87e555781SBibo Mao #ifndef HW_LOONGSON_IPI_COMMON_H 97e555781SBibo Mao #define HW_LOONGSON_IPI_COMMON_H 107e555781SBibo Mao 117e555781SBibo Mao #include "qom/object.h" 127e555781SBibo Mao #include "hw/sysbus.h" 132aca564eSBibo Mao #include "exec/memattrs.h" 147e555781SBibo Mao 156c8698a5SBibo Mao #define IPI_MBX_NUM 4 166c8698a5SBibo Mao 177e555781SBibo Mao #define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common" 187e555781SBibo Mao OBJECT_DECLARE_TYPE(LoongsonIPICommonState, 197e555781SBibo Mao LoongsonIPICommonClass, LOONGSON_IPI_COMMON) 207e555781SBibo Mao 216c8698a5SBibo Mao typedef struct IPICore { 226c8698a5SBibo Mao LoongsonIPICommonState *ipi; 236c8698a5SBibo Mao uint32_t status; 246c8698a5SBibo Mao uint32_t en; 256c8698a5SBibo Mao uint32_t set; 266c8698a5SBibo Mao uint32_t clear; 276c8698a5SBibo Mao /* 64bit buf divide into 2 32-bit buf */ 286c8698a5SBibo Mao uint32_t buf[IPI_MBX_NUM * 2]; 296c8698a5SBibo Mao qemu_irq irq; 3014dc02b5SBibo Mao uint64_t arch_id; 3114dc02b5SBibo Mao CPUState *cpu; 326c8698a5SBibo Mao } IPICore; 336c8698a5SBibo Mao 347e555781SBibo Mao struct LoongsonIPICommonState { 357e555781SBibo Mao SysBusDevice parent_obj; 366c8698a5SBibo Mao 376c8698a5SBibo Mao MemoryRegion ipi_iocsr_mem; 386c8698a5SBibo Mao MemoryRegion ipi64_iocsr_mem; 396c8698a5SBibo Mao uint32_t num_cpu; 406c8698a5SBibo Mao IPICore *cpu; 417e555781SBibo Mao }; 427e555781SBibo Mao 437e555781SBibo Mao struct LoongsonIPICommonClass { 447e555781SBibo Mao SysBusDeviceClass parent_class; 45a81cd679SBibo Mao 46ec859557SBibo Mao DeviceRealize parent_realize; 47ec859557SBibo Mao DeviceUnrealize parent_unrealize; 48a81cd679SBibo Mao AddressSpace *(*get_iocsr_as)(CPUState *cpu); 49*999b112dSBibo Mao int (*cpu_by_arch_id)(LoongsonIPICommonState *lics, int64_t id, 50*999b112dSBibo Mao int *index, CPUState **pcs); 517e555781SBibo Mao }; 527e555781SBibo Mao 532aca564eSBibo Mao MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, 542aca564eSBibo Mao unsigned size, MemTxAttrs attrs); 552aca564eSBibo Mao MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, 562aca564eSBibo Mao unsigned size, MemTxAttrs attrs); 572aca564eSBibo Mao 582252e6c9SBibo Mao /* Mainy used by iocsr read and write */ 592252e6c9SBibo Mao #define SMP_IPI_MAILBOX 0x1000ULL 602252e6c9SBibo Mao 612252e6c9SBibo Mao #define CORE_STATUS_OFF 0x0 622252e6c9SBibo Mao #define CORE_EN_OFF 0x4 632252e6c9SBibo Mao #define CORE_SET_OFF 0x8 642252e6c9SBibo Mao #define CORE_CLEAR_OFF 0xc 652252e6c9SBibo Mao #define CORE_BUF_20 0x20 662252e6c9SBibo Mao #define CORE_BUF_28 0x28 672252e6c9SBibo Mao #define CORE_BUF_30 0x30 682252e6c9SBibo Mao #define CORE_BUF_38 0x38 692252e6c9SBibo Mao #define IOCSR_IPI_SEND 0x40 702252e6c9SBibo Mao #define IOCSR_MAIL_SEND 0x48 712252e6c9SBibo Mao #define IOCSR_ANY_SEND 0x158 722252e6c9SBibo Mao 732252e6c9SBibo Mao #define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) 742252e6c9SBibo Mao #define MAIL_SEND_OFFSET 0 752252e6c9SBibo Mao #define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) 762252e6c9SBibo Mao 777e555781SBibo Mao #endif 78