17e555781SBibo Mao /* SPDX-License-Identifier: GPL-2.0-or-later */ 27e555781SBibo Mao /* 37e555781SBibo Mao * Loongson ipi interrupt header files 47e555781SBibo Mao * 57e555781SBibo Mao * Copyright (C) 2021 Loongson Technology Corporation Limited 67e555781SBibo Mao */ 77e555781SBibo Mao 87e555781SBibo Mao #ifndef HW_LOONGSON_IPI_COMMON_H 97e555781SBibo Mao #define HW_LOONGSON_IPI_COMMON_H 107e555781SBibo Mao 117e555781SBibo Mao #include "qom/object.h" 127e555781SBibo Mao #include "hw/sysbus.h" 13*2aca564eSBibo Mao #include "exec/memattrs.h" 147e555781SBibo Mao 156c8698a5SBibo Mao #define IPI_MBX_NUM 4 166c8698a5SBibo Mao 177e555781SBibo Mao #define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common" 187e555781SBibo Mao OBJECT_DECLARE_TYPE(LoongsonIPICommonState, 197e555781SBibo Mao LoongsonIPICommonClass, LOONGSON_IPI_COMMON) 207e555781SBibo Mao 216c8698a5SBibo Mao typedef struct IPICore { 226c8698a5SBibo Mao LoongsonIPICommonState *ipi; 236c8698a5SBibo Mao uint32_t status; 246c8698a5SBibo Mao uint32_t en; 256c8698a5SBibo Mao uint32_t set; 266c8698a5SBibo Mao uint32_t clear; 276c8698a5SBibo Mao /* 64bit buf divide into 2 32-bit buf */ 286c8698a5SBibo Mao uint32_t buf[IPI_MBX_NUM * 2]; 296c8698a5SBibo Mao qemu_irq irq; 306c8698a5SBibo Mao } IPICore; 316c8698a5SBibo Mao 327e555781SBibo Mao struct LoongsonIPICommonState { 337e555781SBibo Mao SysBusDevice parent_obj; 346c8698a5SBibo Mao 356c8698a5SBibo Mao MemoryRegion ipi_iocsr_mem; 366c8698a5SBibo Mao MemoryRegion ipi64_iocsr_mem; 376c8698a5SBibo Mao uint32_t num_cpu; 386c8698a5SBibo Mao IPICore *cpu; 397e555781SBibo Mao }; 407e555781SBibo Mao 417e555781SBibo Mao struct LoongsonIPICommonClass { 427e555781SBibo Mao SysBusDeviceClass parent_class; 43a81cd679SBibo Mao 44a81cd679SBibo Mao AddressSpace *(*get_iocsr_as)(CPUState *cpu); 458f4f38fdSBibo Mao CPUState *(*cpu_by_arch_id)(int64_t id); 467e555781SBibo Mao }; 477e555781SBibo Mao 48*2aca564eSBibo Mao MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, 49*2aca564eSBibo Mao unsigned size, MemTxAttrs attrs); 50*2aca564eSBibo Mao MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, 51*2aca564eSBibo Mao unsigned size, MemTxAttrs attrs); 52*2aca564eSBibo Mao 532252e6c9SBibo Mao /* Mainy used by iocsr read and write */ 542252e6c9SBibo Mao #define SMP_IPI_MAILBOX 0x1000ULL 552252e6c9SBibo Mao 562252e6c9SBibo Mao #define CORE_STATUS_OFF 0x0 572252e6c9SBibo Mao #define CORE_EN_OFF 0x4 582252e6c9SBibo Mao #define CORE_SET_OFF 0x8 592252e6c9SBibo Mao #define CORE_CLEAR_OFF 0xc 602252e6c9SBibo Mao #define CORE_BUF_20 0x20 612252e6c9SBibo Mao #define CORE_BUF_28 0x28 622252e6c9SBibo Mao #define CORE_BUF_30 0x30 632252e6c9SBibo Mao #define CORE_BUF_38 0x38 642252e6c9SBibo Mao #define IOCSR_IPI_SEND 0x40 652252e6c9SBibo Mao #define IOCSR_MAIL_SEND 0x48 662252e6c9SBibo Mao #define IOCSR_ANY_SEND 0x158 672252e6c9SBibo Mao 682252e6c9SBibo Mao #define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) 692252e6c9SBibo Mao #define MAIL_SEND_OFFSET 0 702252e6c9SBibo Mao #define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) 712252e6c9SBibo Mao 727e555781SBibo Mao #endif 73