1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * LoongArch 3A5000 ext interrupt controller definitions 4 * Copyright (C) 2024 Loongson Technology Corporation Limited 5 */ 6 7 #ifndef LOONGARCH_EXTIOI_COMMON_H 8 #define LOONGARCH_EXTIOI_COMMON_H 9 10 #include "qom/object.h" 11 #include "hw/sysbus.h" 12 #include "hw/loongarch/virt.h" 13 14 #define LS3A_INTC_IP 8 15 #define EXTIOI_IRQS (256) 16 #define EXTIOI_IRQS_BITMAP_SIZE (256 / 8) 17 /* irq from EXTIOI is routed to no more than 4 cpus */ 18 #define EXTIOI_CPUS (4) 19 /* map to ipnum per 32 irqs */ 20 #define EXTIOI_IRQS_IPMAP_SIZE (256 / 32) 21 #define EXTIOI_IRQS_COREMAP_SIZE 256 22 #define EXTIOI_IRQS_NODETYPE_COUNT 16 23 #define EXTIOI_IRQS_GROUP_COUNT 8 24 25 #define APIC_OFFSET 0x400 26 #define APIC_BASE (0x1000ULL + APIC_OFFSET) 27 #define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET) 28 #define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET) 29 #define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET) 30 #define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET) 31 #define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET) 32 #define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET) 33 #define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET) 34 #define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET) 35 #define EXTIOI_ISR_START (0x700 - APIC_OFFSET) 36 #define EXTIOI_ISR_END (0x720 - APIC_OFFSET) 37 #define EXTIOI_COREISR_START (0x800 - APIC_OFFSET) 38 #define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET) 39 #define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET) 40 #define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET) 41 #define EXTIOI_SIZE 0x800 42 43 #define EXTIOI_VIRT_BASE (0x40000000) 44 #define EXTIOI_VIRT_SIZE (0x1000) 45 #define EXTIOI_VIRT_FEATURES (0x0) 46 #define EXTIOI_HAS_VIRT_EXTENSION (0) 47 #define EXTIOI_HAS_ENABLE_OPTION (1) 48 #define EXTIOI_HAS_INT_ENCODE (2) 49 #define EXTIOI_HAS_CPU_ENCODE (3) 50 #define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \ 51 | BIT(EXTIOI_HAS_ENABLE_OPTION) \ 52 | BIT(EXTIOI_HAS_CPU_ENCODE)) 53 #define EXTIOI_VIRT_CONFIG (0x4) 54 #define EXTIOI_ENABLE (1) 55 #define EXTIOI_ENABLE_INT_ENCODE (2) 56 #define EXTIOI_ENABLE_CPU_ENCODE (3) 57 #define EXTIOI_VIRT_COREMAP_START (0x40) 58 #define EXTIOI_VIRT_COREMAP_END (0x240) 59 60 #define TYPE_LOONGARCH_EXTIOI_COMMON "loongarch_extioi_common" 61 OBJECT_DECLARE_TYPE(LoongArchExtIOICommonState, 62 LoongArchExtIOICommonClass, LOONGARCH_EXTIOI_COMMON) 63 64 typedef struct ExtIOICore { 65 uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT]; 66 DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS); 67 qemu_irq parent_irq[LS3A_INTC_IP]; 68 uint64_t arch_id; 69 CPUState *cpu; 70 } ExtIOICore; 71 72 struct LoongArchExtIOICommonState { 73 SysBusDevice parent_obj; 74 uint32_t num_cpu; 75 uint32_t features; 76 uint32_t status; 77 /* hardware state */ 78 uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2]; 79 uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT]; 80 uint32_t isr[EXTIOI_IRQS / 32]; 81 uint32_t enable[EXTIOI_IRQS / 32]; 82 uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4]; 83 uint32_t coremap[EXTIOI_IRQS / 4]; 84 uint32_t sw_pending[EXTIOI_IRQS / 32]; 85 uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE]; 86 uint8_t sw_coremap[EXTIOI_IRQS]; 87 qemu_irq irq[EXTIOI_IRQS]; 88 ExtIOICore *cpu; 89 MemoryRegion extioi_system_mem; 90 MemoryRegion virt_extend; 91 }; 92 93 struct LoongArchExtIOICommonClass { 94 SysBusDeviceClass parent_class; 95 96 DeviceRealize parent_realize; 97 int (*pre_save)(void *s); 98 int (*post_load)(void *s, int version_id); 99 }; 100 #endif /* LOONGARCH_EXTIOI_H */ 101