1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * LoongArch 3A5000 ext interrupt controller definitions 4 * Copyright (C) 2024 Loongson Technology Corporation Limited 5 */ 6 7 #ifndef LOONGARCH_EXTIOI_COMMON_H 8 #define LOONGARCH_EXTIOI_COMMON_H 9 10 #include "hw/sysbus.h" 11 #include "hw/loongarch/virt.h" 12 13 #define LS3A_INTC_IP 8 14 #define EXTIOI_IRQS (256) 15 #define EXTIOI_IRQS_BITMAP_SIZE (256 / 8) 16 /* irq from EXTIOI is routed to no more than 4 cpus */ 17 #define EXTIOI_CPUS (4) 18 /* map to ipnum per 32 irqs */ 19 #define EXTIOI_IRQS_IPMAP_SIZE (256 / 32) 20 #define EXTIOI_IRQS_COREMAP_SIZE 256 21 #define EXTIOI_IRQS_NODETYPE_COUNT 16 22 #define EXTIOI_IRQS_GROUP_COUNT 8 23 24 #define APIC_OFFSET 0x400 25 #define APIC_BASE (0x1000ULL + APIC_OFFSET) 26 #define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET) 27 #define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET) 28 #define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET) 29 #define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET) 30 #define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET) 31 #define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET) 32 #define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET) 33 #define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET) 34 #define EXTIOI_ISR_START (0x700 - APIC_OFFSET) 35 #define EXTIOI_ISR_END (0x720 - APIC_OFFSET) 36 #define EXTIOI_COREISR_START (0x800 - APIC_OFFSET) 37 #define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET) 38 #define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET) 39 #define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET) 40 #define EXTIOI_SIZE 0x800 41 42 #define EXTIOI_VIRT_BASE (0x40000000) 43 #define EXTIOI_VIRT_SIZE (0x1000) 44 #define EXTIOI_VIRT_FEATURES (0x0) 45 #define EXTIOI_HAS_VIRT_EXTENSION (0) 46 #define EXTIOI_HAS_ENABLE_OPTION (1) 47 #define EXTIOI_HAS_INT_ENCODE (2) 48 #define EXTIOI_HAS_CPU_ENCODE (3) 49 #define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \ 50 | BIT(EXTIOI_HAS_ENABLE_OPTION) \ 51 | BIT(EXTIOI_HAS_CPU_ENCODE)) 52 #define EXTIOI_VIRT_CONFIG (0x4) 53 #define EXTIOI_ENABLE (1) 54 #define EXTIOI_ENABLE_INT_ENCODE (2) 55 #define EXTIOI_ENABLE_CPU_ENCODE (3) 56 #define EXTIOI_VIRT_COREMAP_START (0x40) 57 #define EXTIOI_VIRT_COREMAP_END (0x240) 58 59 typedef struct ExtIOICore { 60 uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT]; 61 DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS); 62 qemu_irq parent_irq[LS3A_INTC_IP]; 63 } ExtIOICore; 64 65 struct LoongArchExtIOICommonState { 66 SysBusDevice parent_obj; 67 uint32_t num_cpu; 68 uint32_t features; 69 uint32_t status; 70 /* hardware state */ 71 uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2]; 72 uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT]; 73 uint32_t isr[EXTIOI_IRQS / 32]; 74 uint32_t enable[EXTIOI_IRQS / 32]; 75 uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4]; 76 uint32_t coremap[EXTIOI_IRQS / 4]; 77 uint32_t sw_pending[EXTIOI_IRQS / 32]; 78 uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE]; 79 uint8_t sw_coremap[EXTIOI_IRQS]; 80 qemu_irq irq[EXTIOI_IRQS]; 81 ExtIOICore *cpu; 82 MemoryRegion extioi_system_mem; 83 MemoryRegion virt_extend; 84 }; 85 #endif /* LOONGARCH_EXTIOI_H */ 86