1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * LoongArch 3A5000 ext interrupt controller definitions 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef LOONGARCH_EXTIOI_H 9 #define LOONGARCH_EXTIOI_H 10 11 #include "hw/intc/loongarch_extioi_common.h" 12 13 typedef struct ExtIOICore { 14 uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT]; 15 DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS); 16 qemu_irq parent_irq[LS3A_INTC_IP]; 17 } ExtIOICore; 18 19 #define TYPE_LOONGARCH_EXTIOI "loongarch.extioi" 20 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI) 21 struct LoongArchExtIOI { 22 SysBusDevice parent_obj; 23 uint32_t num_cpu; 24 uint32_t features; 25 uint32_t status; 26 /* hardware state */ 27 uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2]; 28 uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT]; 29 uint32_t isr[EXTIOI_IRQS / 32]; 30 uint32_t enable[EXTIOI_IRQS / 32]; 31 uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4]; 32 uint32_t coremap[EXTIOI_IRQS / 4]; 33 uint32_t sw_pending[EXTIOI_IRQS / 32]; 34 uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE]; 35 uint8_t sw_coremap[EXTIOI_IRQS]; 36 qemu_irq irq[EXTIOI_IRQS]; 37 ExtIOICore *cpu; 38 MemoryRegion extioi_system_mem; 39 MemoryRegion virt_extend; 40 }; 41 #endif /* LOONGARCH_EXTIOI_H */ 42