1*cc28296dSAndrew Baumann /* 2*cc28296dSAndrew Baumann * Raspberry Pi emulation (c) 2012 Gregory Estrade 3*cc28296dSAndrew Baumann * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4*cc28296dSAndrew Baumann * 5*cc28296dSAndrew Baumann * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft 6*cc28296dSAndrew Baumann * Written by Andrew Baumann 7*cc28296dSAndrew Baumann * 8*cc28296dSAndrew Baumann * This code is licensed under the GNU GPLv2 and later. 9*cc28296dSAndrew Baumann */ 10*cc28296dSAndrew Baumann 11*cc28296dSAndrew Baumann #ifndef BCM2836_CONTROL_H 12*cc28296dSAndrew Baumann #define BCM2836_CONTROL_H 13*cc28296dSAndrew Baumann 14*cc28296dSAndrew Baumann #include "hw/sysbus.h" 15*cc28296dSAndrew Baumann 16*cc28296dSAndrew Baumann /* 4 mailboxes per core, for 16 total */ 17*cc28296dSAndrew Baumann #define BCM2836_NCORES 4 18*cc28296dSAndrew Baumann #define BCM2836_MBPERCORE 4 19*cc28296dSAndrew Baumann 20*cc28296dSAndrew Baumann #define TYPE_BCM2836_CONTROL "bcm2836-control" 21*cc28296dSAndrew Baumann #define BCM2836_CONTROL(obj) \ 22*cc28296dSAndrew Baumann OBJECT_CHECK(BCM2836ControlState, (obj), TYPE_BCM2836_CONTROL) 23*cc28296dSAndrew Baumann 24*cc28296dSAndrew Baumann typedef struct BCM2836ControlState { 25*cc28296dSAndrew Baumann /*< private >*/ 26*cc28296dSAndrew Baumann SysBusDevice busdev; 27*cc28296dSAndrew Baumann /*< public >*/ 28*cc28296dSAndrew Baumann MemoryRegion iomem; 29*cc28296dSAndrew Baumann 30*cc28296dSAndrew Baumann /* mailbox state */ 31*cc28296dSAndrew Baumann uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE]; 32*cc28296dSAndrew Baumann 33*cc28296dSAndrew Baumann /* interrupt routing/control registers */ 34*cc28296dSAndrew Baumann uint8_t route_gpu_irq, route_gpu_fiq; 35*cc28296dSAndrew Baumann uint32_t timercontrol[BCM2836_NCORES]; 36*cc28296dSAndrew Baumann uint32_t mailboxcontrol[BCM2836_NCORES]; 37*cc28296dSAndrew Baumann 38*cc28296dSAndrew Baumann /* interrupt status regs (derived from input pins; not visible to user) */ 39*cc28296dSAndrew Baumann bool gpu_irq, gpu_fiq; 40*cc28296dSAndrew Baumann uint8_t timerirqs[BCM2836_NCORES]; 41*cc28296dSAndrew Baumann 42*cc28296dSAndrew Baumann /* interrupt source registers, post-routing (also input-derived; visible) */ 43*cc28296dSAndrew Baumann uint32_t irqsrc[BCM2836_NCORES]; 44*cc28296dSAndrew Baumann uint32_t fiqsrc[BCM2836_NCORES]; 45*cc28296dSAndrew Baumann 46*cc28296dSAndrew Baumann /* outputs to CPU cores */ 47*cc28296dSAndrew Baumann qemu_irq irq[BCM2836_NCORES]; 48*cc28296dSAndrew Baumann qemu_irq fiq[BCM2836_NCORES]; 49*cc28296dSAndrew Baumann } BCM2836ControlState; 50*cc28296dSAndrew Baumann 51*cc28296dSAndrew Baumann #endif 52