1*386ce3c7SPavel Fedin /* 2*386ce3c7SPavel Fedin * ITS support for ARM GICv3 3*386ce3c7SPavel Fedin * 4*386ce3c7SPavel Fedin * Copyright (c) 2015 Samsung Electronics Co., Ltd. 5*386ce3c7SPavel Fedin * Written by Pavel Fedin 6*386ce3c7SPavel Fedin * 7*386ce3c7SPavel Fedin * This program is free software; you can redistribute it and/or modify 8*386ce3c7SPavel Fedin * it under the terms of the GNU General Public License as published by 9*386ce3c7SPavel Fedin * the Free Software Foundation, either version 2 of the License, or 10*386ce3c7SPavel Fedin * (at your option) any later version. 11*386ce3c7SPavel Fedin * 12*386ce3c7SPavel Fedin * This program is distributed in the hope that it will be useful, 13*386ce3c7SPavel Fedin * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*386ce3c7SPavel Fedin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*386ce3c7SPavel Fedin * GNU General Public License for more details. 16*386ce3c7SPavel Fedin * 17*386ce3c7SPavel Fedin * You should have received a copy of the GNU General Public License along 18*386ce3c7SPavel Fedin * with this program; if not, see <http://www.gnu.org/licenses/>. 19*386ce3c7SPavel Fedin */ 20*386ce3c7SPavel Fedin 21*386ce3c7SPavel Fedin #ifndef QEMU_ARM_GICV3_ITS_COMMON_H 22*386ce3c7SPavel Fedin #define QEMU_ARM_GICV3_ITS_COMMON_H 23*386ce3c7SPavel Fedin 24*386ce3c7SPavel Fedin #include "hw/sysbus.h" 25*386ce3c7SPavel Fedin #include "hw/intc/arm_gicv3_common.h" 26*386ce3c7SPavel Fedin 27*386ce3c7SPavel Fedin #define ITS_CONTROL_SIZE 0x10000 28*386ce3c7SPavel Fedin #define ITS_TRANS_SIZE 0x10000 29*386ce3c7SPavel Fedin #define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE) 30*386ce3c7SPavel Fedin 31*386ce3c7SPavel Fedin struct GICv3ITSState { 32*386ce3c7SPavel Fedin SysBusDevice parent_obj; 33*386ce3c7SPavel Fedin 34*386ce3c7SPavel Fedin MemoryRegion iomem_main; 35*386ce3c7SPavel Fedin MemoryRegion iomem_its_cntrl; 36*386ce3c7SPavel Fedin MemoryRegion iomem_its_translation; 37*386ce3c7SPavel Fedin 38*386ce3c7SPavel Fedin GICv3State *gicv3; 39*386ce3c7SPavel Fedin 40*386ce3c7SPavel Fedin int dev_fd; /* kvm device fd if backed by kvm vgic support */ 41*386ce3c7SPavel Fedin uint64_t gits_translater_gpa; 42*386ce3c7SPavel Fedin bool translater_gpa_known; 43*386ce3c7SPavel Fedin 44*386ce3c7SPavel Fedin /* Registers */ 45*386ce3c7SPavel Fedin uint32_t ctlr; 46*386ce3c7SPavel Fedin uint64_t cbaser; 47*386ce3c7SPavel Fedin uint64_t cwriter; 48*386ce3c7SPavel Fedin uint64_t creadr; 49*386ce3c7SPavel Fedin uint64_t baser[8]; 50*386ce3c7SPavel Fedin 51*386ce3c7SPavel Fedin Error *migration_blocker; 52*386ce3c7SPavel Fedin }; 53*386ce3c7SPavel Fedin 54*386ce3c7SPavel Fedin typedef struct GICv3ITSState GICv3ITSState; 55*386ce3c7SPavel Fedin 56*386ce3c7SPavel Fedin void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops); 57*386ce3c7SPavel Fedin 58*386ce3c7SPavel Fedin #define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common" 59*386ce3c7SPavel Fedin #define ARM_GICV3_ITS_COMMON(obj) \ 60*386ce3c7SPavel Fedin OBJECT_CHECK(GICv3ITSState, (obj), TYPE_ARM_GICV3_ITS_COMMON) 61*386ce3c7SPavel Fedin #define ARM_GICV3_ITS_COMMON_CLASS(klass) \ 62*386ce3c7SPavel Fedin OBJECT_CLASS_CHECK(GICv3ITSCommonClass, (klass), TYPE_ARM_GICV3_ITS_COMMON) 63*386ce3c7SPavel Fedin #define ARM_GICV3_ITS_COMMON_GET_CLASS(obj) \ 64*386ce3c7SPavel Fedin OBJECT_GET_CLASS(GICv3ITSCommonClass, (obj), TYPE_ARM_GICV3_ITS_COMMON) 65*386ce3c7SPavel Fedin 66*386ce3c7SPavel Fedin struct GICv3ITSCommonClass { 67*386ce3c7SPavel Fedin /*< private >*/ 68*386ce3c7SPavel Fedin SysBusDeviceClass parent_class; 69*386ce3c7SPavel Fedin /*< public >*/ 70*386ce3c7SPavel Fedin 71*386ce3c7SPavel Fedin int (*send_msi)(GICv3ITSState *s, uint32_t data, uint16_t devid); 72*386ce3c7SPavel Fedin void (*pre_save)(GICv3ITSState *s); 73*386ce3c7SPavel Fedin void (*post_load)(GICv3ITSState *s); 74*386ce3c7SPavel Fedin }; 75*386ce3c7SPavel Fedin 76*386ce3c7SPavel Fedin typedef struct GICv3ITSCommonClass GICv3ITSCommonClass; 77*386ce3c7SPavel Fedin 78*386ce3c7SPavel Fedin #endif 79