1 /* 2 * ARM GIC support 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef HW_ARM_GIC_COMMON_H 22 #define HW_ARM_GIC_COMMON_H 23 24 #include "hw/sysbus.h" 25 26 /* Maximum number of possible interrupts, determined by the GIC architecture */ 27 #define GIC_MAXIRQ 1020 28 /* First 32 are private to each CPU (SGIs and PPIs). */ 29 #define GIC_INTERNAL 32 30 #define GIC_NR_SGIS 16 31 /* Maximum number of possible CPU interfaces, determined by GIC architecture */ 32 #define GIC_NCPU 8 33 34 #define MAX_NR_GROUP_PRIO 128 35 #define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32) 36 37 #define GIC_MIN_BPR 0 38 #define GIC_MIN_ABPR (GIC_MIN_BPR + 1) 39 40 typedef struct gic_irq_state { 41 /* The enable bits are only banked for per-cpu interrupts. */ 42 uint8_t enabled; 43 uint8_t pending; 44 uint8_t active; 45 uint8_t level; 46 bool model; /* 0 = N:N, 1 = 1:N */ 47 bool edge_trigger; /* true: edge-triggered, false: level-triggered */ 48 uint8_t group; 49 } gic_irq_state; 50 51 typedef struct GICState { 52 /*< private >*/ 53 SysBusDevice parent_obj; 54 /*< public >*/ 55 56 qemu_irq parent_irq[GIC_NCPU]; 57 qemu_irq parent_fiq[GIC_NCPU]; 58 /* GICD_CTLR; for a GIC with the security extensions the NS banked version 59 * of this register is just an alias of bit 1 of the S banked version. 60 */ 61 uint32_t ctlr; 62 bool cpu_enabled[GIC_NCPU]; 63 64 gic_irq_state irq_state[GIC_MAXIRQ]; 65 uint8_t irq_target[GIC_MAXIRQ]; 66 uint8_t priority1[GIC_INTERNAL][GIC_NCPU]; 67 uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; 68 uint16_t last_active[GIC_MAXIRQ][GIC_NCPU]; 69 /* For each SGI on the target CPU, we store 8 bits 70 * indicating which source CPUs have made this SGI 71 * pending on the target CPU. These correspond to 72 * the bytes in the GIC_SPENDSGIR* registers as 73 * read by the target CPU. 74 */ 75 uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU]; 76 77 uint16_t priority_mask[GIC_NCPU]; 78 uint16_t running_irq[GIC_NCPU]; 79 uint16_t running_priority[GIC_NCPU]; 80 uint16_t current_pending[GIC_NCPU]; 81 82 /* If we present the GICv2 without security extensions to a guest, 83 * the guest can configure the GICC_CTLR to configure group 1 binary point 84 * in the abpr. 85 * For a GIC with Security Extensions we use use bpr for the 86 * secure copy and abpr as storage for the non-secure copy of the register. 87 */ 88 uint8_t bpr[GIC_NCPU]; 89 uint8_t abpr[GIC_NCPU]; 90 91 /* The APR is implementation defined, so we choose a layout identical to 92 * the KVM ABI layout for QEMU's implementation of the gic: 93 * If an interrupt for preemption level X is active, then 94 * APRn[X mod 32] == 0b1, where n = X / 32 95 * otherwise the bit is clear. 96 * 97 * TODO: rewrite the interrupt acknowlege/complete routines to use 98 * the APR registers to track the necessary information to update 99 * s->running_priority[] on interrupt completion (ie completely remove 100 * last_active[][] and running_irq[]). This will be necessary if we ever 101 * want to support TCG<->KVM migration, or TCG guests which can 102 * do power management involving powering down and restarting 103 * the GIC. 104 */ 105 uint32_t apr[GIC_NR_APRS][GIC_NCPU]; 106 107 uint32_t num_cpu; 108 109 MemoryRegion iomem; /* Distributor */ 110 /* This is just so we can have an opaque pointer which identifies 111 * both this GIC and which CPU interface we should be accessing. 112 */ 113 struct GICState *backref[GIC_NCPU]; 114 MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ 115 uint32_t num_irq; 116 uint32_t revision; 117 bool security_extn; 118 int dev_fd; /* kvm device fd if backed by kvm vgic support */ 119 } GICState; 120 121 #define TYPE_ARM_GIC_COMMON "arm_gic_common" 122 #define ARM_GIC_COMMON(obj) \ 123 OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON) 124 #define ARM_GIC_COMMON_CLASS(klass) \ 125 OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON) 126 #define ARM_GIC_COMMON_GET_CLASS(obj) \ 127 OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON) 128 129 typedef struct ARMGICCommonClass { 130 /*< private >*/ 131 SysBusDeviceClass parent_class; 132 /*< public >*/ 133 134 void (*pre_save)(GICState *s); 135 void (*post_load)(GICState *s); 136 } ARMGICCommonClass; 137 138 #endif 139