1 /* 2 * ARM GIC support 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef HW_ARM_GIC_COMMON_H 22 #define HW_ARM_GIC_COMMON_H 23 24 #include "hw/sysbus.h" 25 26 /* Maximum number of possible interrupts, determined by the GIC architecture */ 27 #define GIC_MAXIRQ 1020 28 /* First 32 are private to each CPU (SGIs and PPIs). */ 29 #define GIC_INTERNAL 32 30 #define GIC_NR_SGIS 16 31 /* Maximum number of possible CPU interfaces, determined by GIC architecture */ 32 #define GIC_NCPU 8 33 34 #define MAX_NR_GROUP_PRIO 128 35 #define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32) 36 37 typedef struct gic_irq_state { 38 /* The enable bits are only banked for per-cpu interrupts. */ 39 uint8_t enabled; 40 uint8_t pending; 41 uint8_t active; 42 uint8_t level; 43 bool model; /* 0 = N:N, 1 = 1:N */ 44 bool edge_trigger; /* true: edge-triggered, false: level-triggered */ 45 uint8_t group; 46 } gic_irq_state; 47 48 typedef struct GICState { 49 /*< private >*/ 50 SysBusDevice parent_obj; 51 /*< public >*/ 52 53 qemu_irq parent_irq[GIC_NCPU]; 54 qemu_irq parent_fiq[GIC_NCPU]; 55 /* GICD_CTLR; for a GIC with the security extensions the NS banked version 56 * of this register is just an alias of bit 1 of the S banked version. 57 */ 58 uint32_t ctlr; 59 bool cpu_enabled[GIC_NCPU]; 60 61 gic_irq_state irq_state[GIC_MAXIRQ]; 62 uint8_t irq_target[GIC_MAXIRQ]; 63 uint8_t priority1[GIC_INTERNAL][GIC_NCPU]; 64 uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; 65 uint16_t last_active[GIC_MAXIRQ][GIC_NCPU]; 66 /* For each SGI on the target CPU, we store 8 bits 67 * indicating which source CPUs have made this SGI 68 * pending on the target CPU. These correspond to 69 * the bytes in the GIC_SPENDSGIR* registers as 70 * read by the target CPU. 71 */ 72 uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU]; 73 74 uint16_t priority_mask[GIC_NCPU]; 75 uint16_t running_irq[GIC_NCPU]; 76 uint16_t running_priority[GIC_NCPU]; 77 uint16_t current_pending[GIC_NCPU]; 78 79 /* We present the GICv2 without security extensions to a guest and 80 * therefore the guest can configure the GICC_CTLR to configure group 1 81 * binary point in the abpr. 82 */ 83 uint8_t bpr[GIC_NCPU]; 84 uint8_t abpr[GIC_NCPU]; 85 86 /* The APR is implementation defined, so we choose a layout identical to 87 * the KVM ABI layout for QEMU's implementation of the gic: 88 * If an interrupt for preemption level X is active, then 89 * APRn[X mod 32] == 0b1, where n = X / 32 90 * otherwise the bit is clear. 91 * 92 * TODO: rewrite the interrupt acknowlege/complete routines to use 93 * the APR registers to track the necessary information to update 94 * s->running_priority[] on interrupt completion (ie completely remove 95 * last_active[][] and running_irq[]). This will be necessary if we ever 96 * want to support TCG<->KVM migration, or TCG guests which can 97 * do power management involving powering down and restarting 98 * the GIC. 99 */ 100 uint32_t apr[GIC_NR_APRS][GIC_NCPU]; 101 102 uint32_t num_cpu; 103 104 MemoryRegion iomem; /* Distributor */ 105 /* This is just so we can have an opaque pointer which identifies 106 * both this GIC and which CPU interface we should be accessing. 107 */ 108 struct GICState *backref[GIC_NCPU]; 109 MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ 110 uint32_t num_irq; 111 uint32_t revision; 112 bool security_extn; 113 int dev_fd; /* kvm device fd if backed by kvm vgic support */ 114 } GICState; 115 116 #define TYPE_ARM_GIC_COMMON "arm_gic_common" 117 #define ARM_GIC_COMMON(obj) \ 118 OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON) 119 #define ARM_GIC_COMMON_CLASS(klass) \ 120 OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON) 121 #define ARM_GIC_COMMON_GET_CLASS(obj) \ 122 OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON) 123 124 typedef struct ARMGICCommonClass { 125 /*< private >*/ 126 SysBusDeviceClass parent_class; 127 /*< public >*/ 128 129 void (*pre_save)(GICState *s); 130 void (*post_load)(GICState *s); 131 } ARMGICCommonClass; 132 133 #endif 134