1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu/notify.h" 5 #include "qapi/qapi-types-common.h" 6 #include "qemu/uuid.h" 7 #include "hw/boards.h" 8 #include "hw/block/fdc.h" 9 #include "hw/block/flash.h" 10 #include "hw/i386/x86.h" 11 12 #include "hw/hotplug.h" 13 #include "qom/object.h" 14 #include "hw/i386/sgx-epc.h" 15 #include "hw/cxl/cxl.h" 16 17 #define MAX_IDE_BUS 2 18 19 /** 20 * PCMachineState: 21 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 22 * @boot_cpus: number of present VCPUs 23 */ 24 typedef struct PCMachineState { 25 /*< private >*/ 26 X86MachineState parent_obj; 27 28 /* <public> */ 29 30 /* State for other subsystems/APIs: */ 31 Notifier machine_done; 32 33 /* Pointers to devices and objects: */ 34 PCIBus *pcibus; 35 I2CBus *smbus; 36 PFlashCFI01 *flash[2]; 37 ISADevice *pcspk; 38 DeviceState *iommu; 39 BusState *idebus[MAX_IDE_BUS]; 40 41 /* Configuration options: */ 42 uint64_t max_ram_below_4g; 43 OnOffAuto vmport; 44 SmbiosEntryPointType smbios_entry_point_type; 45 const char *south_bridge; 46 47 bool acpi_build_enabled; 48 bool smbus_enabled; 49 bool sata_enabled; 50 bool hpet_enabled; 51 bool i8042_enabled; 52 bool default_bus_bypass_iommu; 53 bool fd_bootchk; 54 uint64_t max_fw_size; 55 56 /* ACPI Memory hotplug IO base address */ 57 hwaddr memhp_io_base; 58 59 SGXEPCState sgx_epc; 60 CXLState cxl_devices_state; 61 } PCMachineState; 62 63 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 64 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 65 #define PC_MACHINE_VMPORT "vmport" 66 #define PC_MACHINE_SMBUS "smbus" 67 #define PC_MACHINE_SATA "sata" 68 #define PC_MACHINE_I8042 "i8042" 69 #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" 70 #define PC_MACHINE_SMBIOS_EP "smbios-entry-point-type" 71 72 /** 73 * PCMachineClass: 74 * 75 * Compat fields: 76 * 77 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by 78 * backend's alignment value if provided 79 * @acpi_data_size: Size of the chunk of memory at the top of RAM 80 * for the BIOS ACPI tables and other BIOS 81 * datastructures. 82 * @gigabyte_align: Make sure that guest addresses aligned at 83 * 1Gbyte boundaries get mapped to host 84 * addresses aligned at 1Gbyte boundaries. This 85 * way we can use 1GByte pages in the host. 86 * 87 */ 88 struct PCMachineClass { 89 /*< private >*/ 90 X86MachineClass parent_class; 91 92 /*< public >*/ 93 94 /* Device configuration: */ 95 bool pci_enabled; 96 const char *default_south_bridge; 97 98 /* Compat options: */ 99 100 /* Default CPU model version. See x86_cpu_set_default_version(). */ 101 int default_cpu_version; 102 103 /* ACPI compat: */ 104 bool has_acpi_build; 105 bool rsdp_in_ram; 106 unsigned acpi_data_size; 107 int pci_root_uid; 108 109 /* SMBIOS compat: */ 110 bool smbios_defaults; 111 bool smbios_legacy_mode; 112 SmbiosEntryPointType default_smbios_ep_type; 113 114 /* RAM / address space compat: */ 115 bool gigabyte_align; 116 bool has_reserved_memory; 117 bool enforce_aligned_dimm; 118 bool broken_reserved_end; 119 bool enforce_amd_1tb_hole; 120 bool isa_bios_alias; 121 122 /* generate legacy CPU hotplug AML */ 123 bool legacy_cpu_hotplug; 124 125 /* use PVH to load kernels that support this feature */ 126 bool pvh_enabled; 127 128 /* create kvmclock device even when KVM PV features are not exposed */ 129 bool kvmclock_create_always; 130 131 /* resizable acpi blob compat */ 132 bool resizable_acpi_blob; 133 134 /* 135 * whether the machine type implements broken 32-bit address space bound 136 * check for memory. 137 */ 138 bool broken_32bit_mem_addr_check; 139 }; 140 141 #define TYPE_PC_MACHINE "generic-pc-machine" 142 OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE) 143 144 /* ioapic.c */ 145 146 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled); 147 148 /* pc.c */ 149 150 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 151 152 #define PCI_HOST_PROP_RAM_MEM "ram-mem" 153 #define PCI_HOST_PROP_PCI_MEM "pci-mem" 154 #define PCI_HOST_PROP_SYSTEM_MEM "system-mem" 155 #define PCI_HOST_PROP_IO_MEM "io-mem" 156 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 157 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 158 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 159 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 160 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 161 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" 162 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" 163 #define PCI_HOST_PROP_SMM_RANGES "smm-ranges" 164 165 typedef enum { 166 SEV_DESC_TYPE_UNDEF, 167 /* The section contains the region that must be validated by the VMM. */ 168 SEV_DESC_TYPE_SNP_SEC_MEM, 169 /* The section contains the SNP secrets page */ 170 SEV_DESC_TYPE_SNP_SECRETS, 171 /* The section contains address that can be used as a CPUID page */ 172 SEV_DESC_TYPE_CPUID, 173 /* The section contains the region for kernel hashes for measured direct boot */ 174 SEV_DESC_TYPE_SNP_KERNEL_HASHES = 0x10, 175 176 } ovmf_sev_metadata_desc_type; 177 178 typedef struct __attribute__((__packed__)) OvmfSevMetadataDesc { 179 uint32_t base; 180 uint32_t len; 181 ovmf_sev_metadata_desc_type type; 182 } OvmfSevMetadataDesc; 183 184 typedef struct __attribute__((__packed__)) OvmfSevMetadata { 185 uint8_t signature[4]; 186 uint32_t len; 187 uint32_t version; 188 uint32_t num_desc; 189 OvmfSevMetadataDesc descs[]; 190 } OvmfSevMetadata; 191 192 OvmfSevMetadata *pc_system_get_ovmf_sev_metadata_ptr(void); 193 194 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 195 MemoryRegion *pci_address_space); 196 197 void xen_load_linux(PCMachineState *pcms); 198 void pc_memory_init(PCMachineState *pcms, 199 MemoryRegion *system_memory, 200 MemoryRegion *rom_memory, 201 uint64_t pci_hole64_size); 202 uint64_t pc_pci_hole64_start(void); 203 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 204 void pc_basic_device_init(struct PCMachineState *pcms, 205 ISABus *isa_bus, qemu_irq *gsi, 206 ISADevice *rtc_state, 207 bool create_fdctrl, 208 uint32_t hpet_irqs); 209 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); 210 211 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs); 212 213 /* port92.c */ 214 #define PORT92_A20_LINE "a20" 215 216 #define TYPE_PORT92 "port92" 217 218 /* pc_sysfw.c */ 219 void pc_system_flash_create(PCMachineState *pcms); 220 void pc_system_flash_cleanup_unused(PCMachineState *pcms); 221 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); 222 bool pc_system_ovmf_table_find(const char *entry, uint8_t **data, 223 int *data_len); 224 void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size); 225 226 /* sgx.c */ 227 void pc_machine_init_sgx_epc(PCMachineState *pcms); 228 229 extern GlobalProperty pc_compat_9_0[]; 230 extern const size_t pc_compat_9_0_len; 231 232 extern GlobalProperty pc_compat_8_2[]; 233 extern const size_t pc_compat_8_2_len; 234 235 extern GlobalProperty pc_compat_8_1[]; 236 extern const size_t pc_compat_8_1_len; 237 238 extern GlobalProperty pc_compat_8_0[]; 239 extern const size_t pc_compat_8_0_len; 240 241 extern GlobalProperty pc_compat_7_2[]; 242 extern const size_t pc_compat_7_2_len; 243 244 extern GlobalProperty pc_compat_7_1[]; 245 extern const size_t pc_compat_7_1_len; 246 247 extern GlobalProperty pc_compat_7_0[]; 248 extern const size_t pc_compat_7_0_len; 249 250 extern GlobalProperty pc_compat_6_2[]; 251 extern const size_t pc_compat_6_2_len; 252 253 extern GlobalProperty pc_compat_6_1[]; 254 extern const size_t pc_compat_6_1_len; 255 256 extern GlobalProperty pc_compat_6_0[]; 257 extern const size_t pc_compat_6_0_len; 258 259 extern GlobalProperty pc_compat_5_2[]; 260 extern const size_t pc_compat_5_2_len; 261 262 extern GlobalProperty pc_compat_5_1[]; 263 extern const size_t pc_compat_5_1_len; 264 265 extern GlobalProperty pc_compat_5_0[]; 266 extern const size_t pc_compat_5_0_len; 267 268 extern GlobalProperty pc_compat_4_2[]; 269 extern const size_t pc_compat_4_2_len; 270 271 extern GlobalProperty pc_compat_4_1[]; 272 extern const size_t pc_compat_4_1_len; 273 274 extern GlobalProperty pc_compat_4_0[]; 275 extern const size_t pc_compat_4_0_len; 276 277 extern GlobalProperty pc_compat_3_1[]; 278 extern const size_t pc_compat_3_1_len; 279 280 extern GlobalProperty pc_compat_3_0[]; 281 extern const size_t pc_compat_3_0_len; 282 283 extern GlobalProperty pc_compat_2_12[]; 284 extern const size_t pc_compat_2_12_len; 285 286 extern GlobalProperty pc_compat_2_11[]; 287 extern const size_t pc_compat_2_11_len; 288 289 extern GlobalProperty pc_compat_2_10[]; 290 extern const size_t pc_compat_2_10_len; 291 292 extern GlobalProperty pc_compat_2_9[]; 293 extern const size_t pc_compat_2_9_len; 294 295 extern GlobalProperty pc_compat_2_8[]; 296 extern const size_t pc_compat_2_8_len; 297 298 extern GlobalProperty pc_compat_2_7[]; 299 extern const size_t pc_compat_2_7_len; 300 301 extern GlobalProperty pc_compat_2_6[]; 302 extern const size_t pc_compat_2_6_len; 303 304 extern GlobalProperty pc_compat_2_5[]; 305 extern const size_t pc_compat_2_5_len; 306 307 extern GlobalProperty pc_compat_2_4[]; 308 extern const size_t pc_compat_2_4_len; 309 310 extern GlobalProperty pc_compat_2_3[]; 311 extern const size_t pc_compat_2_3_len; 312 313 extern GlobalProperty pc_compat_2_2[]; 314 extern const size_t pc_compat_2_2_len; 315 316 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ 317 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ 318 { \ 319 MachineClass *mc = MACHINE_CLASS(oc); \ 320 optsfn(mc); \ 321 mc->init = initfn; \ 322 } \ 323 static const TypeInfo pc_machine_type_##suffix = { \ 324 .name = namestr TYPE_MACHINE_SUFFIX, \ 325 .parent = TYPE_PC_MACHINE, \ 326 .class_init = pc_machine_##suffix##_class_init, \ 327 }; \ 328 static void pc_machine_init_##suffix(void) \ 329 { \ 330 type_register(&pc_machine_type_##suffix); \ 331 } \ 332 type_init(pc_machine_init_##suffix) 333 334 #endif 335