xref: /qemu/include/hw/i386/apic.h (revision 5767815218efd3cbfd409505ed824d5f356044ae)
1aa28b9bfSBlue Swirl #ifndef APIC_H
2aa28b9bfSBlue Swirl #define APIC_H
3aa28b9bfSBlue Swirl 
492a16d7aSBlue Swirl 
5cf6d64bfSBlue Swirl /* apic.c */
6b5ee0468SBui Quang Minh void apic_set_max_apic_id(uint32_t max_apic_id);
792a16d7aSBlue Swirl int apic_accept_pic_intr(DeviceState *s);
892a16d7aSBlue Swirl void apic_deliver_pic_intr(DeviceState *s, int level);
902c09195SJan Kiszka void apic_deliver_nmi(DeviceState *d);
1092a16d7aSBlue Swirl int apic_get_interrupt(DeviceState *s);
11774204cfSBui Quang Minh int cpu_set_apic_base(DeviceState *s, uint64_t val);
1292a16d7aSBlue Swirl uint64_t cpu_get_apic_base(DeviceState *s);
13*c2e6d7d8SBernhard Beschow bool cpu_is_apic_enabled(DeviceState *s);
1492a16d7aSBlue Swirl void cpu_set_apic_tpr(DeviceState *s, uint8_t val);
1592a16d7aSBlue Swirl uint8_t cpu_get_apic_tpr(DeviceState *s);
1692a16d7aSBlue Swirl void apic_init_reset(DeviceState *s);
1792a16d7aSBlue Swirl void apic_sipi(DeviceState *s);
185d62c43aSJan Kiszka void apic_poll_irq(DeviceState *d);
199cb11fd7SNadav Amit void apic_designate_bsp(DeviceState *d, bool bsp);
202cb9f06eSSergio Andres Gomez Del Real int apic_get_highest_priority_irr(DeviceState *dev);
21b2101358SBui Quang Minh int apic_msr_read(int index, uint64_t *val);
22b2101358SBui Quang Minh int apic_msr_write(int index, uint64_t val);
23b2101358SBui Quang Minh bool is_x2apic_mode(DeviceState *d);
24aa28b9bfSBlue Swirl 
250e26b7b8SBlue Swirl /* pc.c */
2692a16d7aSBlue Swirl DeviceState *cpu_get_current_apic(void);
27aa28b9bfSBlue Swirl 
28aa28b9bfSBlue Swirl #endif
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