1 /* 2 * Nuvoton NPCM7xx SMBus Module. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 #ifndef NPCM7XX_SMBUS_H 17 #define NPCM7XX_SMBUS_H 18 19 #include "exec/memory.h" 20 #include "hw/i2c/i2c.h" 21 #include "hw/irq.h" 22 #include "hw/sysbus.h" 23 24 /* 25 * Number of addresses this module contains. Do not change this without 26 * incrementing the version_id in the vmstate. 27 */ 28 #define NPCM7XX_SMBUS_NR_ADDRS 10 29 30 typedef enum NPCM7xxSMBusStatus { 31 NPCM7XX_SMBUS_STATUS_IDLE, 32 NPCM7XX_SMBUS_STATUS_SENDING, 33 NPCM7XX_SMBUS_STATUS_RECEIVING, 34 NPCM7XX_SMBUS_STATUS_NEGACK, 35 NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE, 36 NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK, 37 } NPCM7xxSMBusStatus; 38 39 /* 40 * struct NPCM7xxSMBusState - System Management Bus device state. 41 * @bus: The underlying I2C Bus. 42 * @irq: GIC interrupt line to fire on events (if enabled). 43 * @sda: The serial data register. 44 * @st: The status register. 45 * @cst: The control status register. 46 * @cst2: The control status register 2. 47 * @cst3: The control status register 3. 48 * @ctl1: The control register 1. 49 * @ctl2: The control register 2. 50 * @ctl3: The control register 3. 51 * @ctl4: The control register 4. 52 * @ctl5: The control register 5. 53 * @addr: The SMBus module's own addresses on the I2C bus. 54 * @scllt: The SCL low time register. 55 * @sclht: The SCL high time register. 56 * @status: The current status of the SMBus. 57 */ 58 typedef struct NPCM7xxSMBusState { 59 SysBusDevice parent; 60 61 MemoryRegion iomem; 62 63 I2CBus *bus; 64 qemu_irq irq; 65 66 uint8_t sda; 67 uint8_t st; 68 uint8_t cst; 69 uint8_t cst2; 70 uint8_t cst3; 71 uint8_t ctl1; 72 uint8_t ctl2; 73 uint8_t ctl3; 74 uint8_t ctl4; 75 uint8_t ctl5; 76 uint8_t addr[NPCM7XX_SMBUS_NR_ADDRS]; 77 78 uint8_t scllt; 79 uint8_t sclht; 80 81 NPCM7xxSMBusStatus status; 82 } NPCM7xxSMBusState; 83 84 #define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus" 85 #define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \ 86 TYPE_NPCM7XX_SMBUS) 87 88 #endif /* NPCM7XX_SMBUS_H */ 89