1*94e77879SHao Wu /* 2*94e77879SHao Wu * Nuvoton NPCM7xx SMBus Module. 3*94e77879SHao Wu * 4*94e77879SHao Wu * Copyright 2020 Google LLC 5*94e77879SHao Wu * 6*94e77879SHao Wu * This program is free software; you can redistribute it and/or modify it 7*94e77879SHao Wu * under the terms of the GNU General Public License as published by the 8*94e77879SHao Wu * Free Software Foundation; either version 2 of the License, or 9*94e77879SHao Wu * (at your option) any later version. 10*94e77879SHao Wu * 11*94e77879SHao Wu * This program is distributed in the hope that it will be useful, but WITHOUT 12*94e77879SHao Wu * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13*94e77879SHao Wu * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14*94e77879SHao Wu * for more details. 15*94e77879SHao Wu */ 16*94e77879SHao Wu #ifndef NPCM7XX_SMBUS_H 17*94e77879SHao Wu #define NPCM7XX_SMBUS_H 18*94e77879SHao Wu 19*94e77879SHao Wu #include "exec/memory.h" 20*94e77879SHao Wu #include "hw/i2c/i2c.h" 21*94e77879SHao Wu #include "hw/irq.h" 22*94e77879SHao Wu #include "hw/sysbus.h" 23*94e77879SHao Wu 24*94e77879SHao Wu /* 25*94e77879SHao Wu * Number of addresses this module contains. Do not change this without 26*94e77879SHao Wu * incrementing the version_id in the vmstate. 27*94e77879SHao Wu */ 28*94e77879SHao Wu #define NPCM7XX_SMBUS_NR_ADDRS 10 29*94e77879SHao Wu 30*94e77879SHao Wu typedef enum NPCM7xxSMBusStatus { 31*94e77879SHao Wu NPCM7XX_SMBUS_STATUS_IDLE, 32*94e77879SHao Wu NPCM7XX_SMBUS_STATUS_SENDING, 33*94e77879SHao Wu NPCM7XX_SMBUS_STATUS_RECEIVING, 34*94e77879SHao Wu NPCM7XX_SMBUS_STATUS_NEGACK, 35*94e77879SHao Wu NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE, 36*94e77879SHao Wu NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK, 37*94e77879SHao Wu } NPCM7xxSMBusStatus; 38*94e77879SHao Wu 39*94e77879SHao Wu /* 40*94e77879SHao Wu * struct NPCM7xxSMBusState - System Management Bus device state. 41*94e77879SHao Wu * @bus: The underlying I2C Bus. 42*94e77879SHao Wu * @irq: GIC interrupt line to fire on events (if enabled). 43*94e77879SHao Wu * @sda: The serial data register. 44*94e77879SHao Wu * @st: The status register. 45*94e77879SHao Wu * @cst: The control status register. 46*94e77879SHao Wu * @cst2: The control status register 2. 47*94e77879SHao Wu * @cst3: The control status register 3. 48*94e77879SHao Wu * @ctl1: The control register 1. 49*94e77879SHao Wu * @ctl2: The control register 2. 50*94e77879SHao Wu * @ctl3: The control register 3. 51*94e77879SHao Wu * @ctl4: The control register 4. 52*94e77879SHao Wu * @ctl5: The control register 5. 53*94e77879SHao Wu * @addr: The SMBus module's own addresses on the I2C bus. 54*94e77879SHao Wu * @scllt: The SCL low time register. 55*94e77879SHao Wu * @sclht: The SCL high time register. 56*94e77879SHao Wu * @status: The current status of the SMBus. 57*94e77879SHao Wu */ 58*94e77879SHao Wu typedef struct NPCM7xxSMBusState { 59*94e77879SHao Wu SysBusDevice parent; 60*94e77879SHao Wu 61*94e77879SHao Wu MemoryRegion iomem; 62*94e77879SHao Wu 63*94e77879SHao Wu I2CBus *bus; 64*94e77879SHao Wu qemu_irq irq; 65*94e77879SHao Wu 66*94e77879SHao Wu uint8_t sda; 67*94e77879SHao Wu uint8_t st; 68*94e77879SHao Wu uint8_t cst; 69*94e77879SHao Wu uint8_t cst2; 70*94e77879SHao Wu uint8_t cst3; 71*94e77879SHao Wu uint8_t ctl1; 72*94e77879SHao Wu uint8_t ctl2; 73*94e77879SHao Wu uint8_t ctl3; 74*94e77879SHao Wu uint8_t ctl4; 75*94e77879SHao Wu uint8_t ctl5; 76*94e77879SHao Wu uint8_t addr[NPCM7XX_SMBUS_NR_ADDRS]; 77*94e77879SHao Wu 78*94e77879SHao Wu uint8_t scllt; 79*94e77879SHao Wu uint8_t sclht; 80*94e77879SHao Wu 81*94e77879SHao Wu NPCM7xxSMBusStatus status; 82*94e77879SHao Wu } NPCM7xxSMBusState; 83*94e77879SHao Wu 84*94e77879SHao Wu #define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus" 85*94e77879SHao Wu #define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \ 86*94e77879SHao Wu TYPE_NPCM7XX_SMBUS) 87*94e77879SHao Wu 88*94e77879SHao Wu #endif /* NPCM7XX_SMBUS_H */ 89