1526dbbe0SHavard Skinnemoen /* 2526dbbe0SHavard Skinnemoen * Nuvoton NPCM7xx General Purpose Input / Output (GPIO) 3526dbbe0SHavard Skinnemoen * 4526dbbe0SHavard Skinnemoen * Copyright 2020 Google LLC 5526dbbe0SHavard Skinnemoen * 6526dbbe0SHavard Skinnemoen * This program is free software; you can redistribute it and/or 7526dbbe0SHavard Skinnemoen * modify it under the terms of the GNU General Public License 8526dbbe0SHavard Skinnemoen * version 2 as published by the Free Software Foundation. 9526dbbe0SHavard Skinnemoen * 10526dbbe0SHavard Skinnemoen * This program is distributed in the hope that it will be useful, 11526dbbe0SHavard Skinnemoen * but WITHOUT ANY WARRANTY; without even the implied warranty of 12526dbbe0SHavard Skinnemoen * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13526dbbe0SHavard Skinnemoen * GNU General Public License for more details. 14526dbbe0SHavard Skinnemoen */ 15526dbbe0SHavard Skinnemoen #ifndef NPCM7XX_GPIO_H 16526dbbe0SHavard Skinnemoen #define NPCM7XX_GPIO_H 17526dbbe0SHavard Skinnemoen 18*8be545baSRichard Henderson #include "system/memory.h" 19526dbbe0SHavard Skinnemoen #include "hw/sysbus.h" 20526dbbe0SHavard Skinnemoen 21526dbbe0SHavard Skinnemoen /* Number of pins managed by each controller. */ 22526dbbe0SHavard Skinnemoen #define NPCM7XX_GPIO_NR_PINS (32) 23526dbbe0SHavard Skinnemoen 24526dbbe0SHavard Skinnemoen /* 25526dbbe0SHavard Skinnemoen * Number of registers in our device state structure. Don't change this without 26526dbbe0SHavard Skinnemoen * incrementing the version_id in the vmstate. 27526dbbe0SHavard Skinnemoen */ 28526dbbe0SHavard Skinnemoen #define NPCM7XX_GPIO_NR_REGS (0x80 / sizeof(uint32_t)) 29526dbbe0SHavard Skinnemoen 30526dbbe0SHavard Skinnemoen typedef struct NPCM7xxGPIOState { 31526dbbe0SHavard Skinnemoen SysBusDevice parent; 32526dbbe0SHavard Skinnemoen 33526dbbe0SHavard Skinnemoen /* Properties to be defined by the SoC */ 34526dbbe0SHavard Skinnemoen uint32_t reset_pu; 35526dbbe0SHavard Skinnemoen uint32_t reset_pd; 36526dbbe0SHavard Skinnemoen uint32_t reset_osrc; 37526dbbe0SHavard Skinnemoen uint32_t reset_odsc; 38526dbbe0SHavard Skinnemoen 39526dbbe0SHavard Skinnemoen MemoryRegion mmio; 40526dbbe0SHavard Skinnemoen 41526dbbe0SHavard Skinnemoen qemu_irq irq; 42526dbbe0SHavard Skinnemoen qemu_irq output[NPCM7XX_GPIO_NR_PINS]; 43526dbbe0SHavard Skinnemoen 44526dbbe0SHavard Skinnemoen uint32_t pin_level; 45526dbbe0SHavard Skinnemoen uint32_t ext_level; 46526dbbe0SHavard Skinnemoen uint32_t ext_driven; 47526dbbe0SHavard Skinnemoen 48526dbbe0SHavard Skinnemoen uint32_t regs[NPCM7XX_GPIO_NR_REGS]; 49526dbbe0SHavard Skinnemoen } NPCM7xxGPIOState; 50526dbbe0SHavard Skinnemoen 51526dbbe0SHavard Skinnemoen #define TYPE_NPCM7XX_GPIO "npcm7xx-gpio" 52526dbbe0SHavard Skinnemoen #define NPCM7XX_GPIO(obj) \ 53526dbbe0SHavard Skinnemoen OBJECT_CHECK(NPCM7xxGPIOState, (obj), TYPE_NPCM7XX_GPIO) 54526dbbe0SHavard Skinnemoen 55526dbbe0SHavard Skinnemoen #endif /* NPCM7XX_GPIO_H */ 56