xref: /qemu/include/hw/gpio/aspeed_gpio.h (revision 4b7f956862dc2db4c5c60762abcb3b6179751cc6) 
1*4b7f9568SRashmica Gupta /*
2*4b7f9568SRashmica Gupta  *  ASPEED GPIO Controller
3*4b7f9568SRashmica Gupta  *
4*4b7f9568SRashmica Gupta  *  Copyright (C) 2017-2018 IBM Corp.
5*4b7f9568SRashmica Gupta  *
6*4b7f9568SRashmica Gupta  * This code is licensed under the GPL version 2 or later.  See
7*4b7f9568SRashmica Gupta  * the COPYING file in the top-level directory.
8*4b7f9568SRashmica Gupta  */
9*4b7f9568SRashmica Gupta 
10*4b7f9568SRashmica Gupta #ifndef ASPEED_GPIO_H
11*4b7f9568SRashmica Gupta #define ASPEED_GPIO_H
12*4b7f9568SRashmica Gupta 
13*4b7f9568SRashmica Gupta #include "hw/sysbus.h"
14*4b7f9568SRashmica Gupta 
15*4b7f9568SRashmica Gupta #define TYPE_ASPEED_GPIO "aspeed.gpio"
16*4b7f9568SRashmica Gupta #define ASPEED_GPIO(obj) OBJECT_CHECK(AspeedGPIOState, (obj), TYPE_ASPEED_GPIO)
17*4b7f9568SRashmica Gupta #define ASPEED_GPIO_CLASS(klass) \
18*4b7f9568SRashmica Gupta      OBJECT_CLASS_CHECK(AspeedGPIOClass, (klass), TYPE_ASPEED_GPIO)
19*4b7f9568SRashmica Gupta #define ASPEED_GPIO_GET_CLASS(obj) \
20*4b7f9568SRashmica Gupta      OBJECT_GET_CLASS(AspeedGPIOClass, (obj), TYPE_ASPEED_GPIO)
21*4b7f9568SRashmica Gupta 
22*4b7f9568SRashmica Gupta #define ASPEED_GPIO_MAX_NR_SETS 8
23*4b7f9568SRashmica Gupta #define ASPEED_REGS_PER_BANK 14
24*4b7f9568SRashmica Gupta #define ASPEED_GPIO_MAX_NR_REGS (ASPEED_REGS_PER_BANK * ASPEED_GPIO_MAX_NR_SETS)
25*4b7f9568SRashmica Gupta #define ASPEED_GPIO_NR_PINS 228
26*4b7f9568SRashmica Gupta #define ASPEED_GROUPS_PER_SET 4
27*4b7f9568SRashmica Gupta #define ASPEED_GPIO_NR_DEBOUNCE_REGS 3
28*4b7f9568SRashmica Gupta #define ASPEED_CHARS_PER_GROUP_LABEL 4
29*4b7f9568SRashmica Gupta 
30*4b7f9568SRashmica Gupta typedef struct GPIOSets GPIOSets;
31*4b7f9568SRashmica Gupta 
32*4b7f9568SRashmica Gupta typedef struct GPIOSetProperties {
33*4b7f9568SRashmica Gupta     uint32_t input;
34*4b7f9568SRashmica Gupta     uint32_t output;
35*4b7f9568SRashmica Gupta     char group_label[ASPEED_GROUPS_PER_SET][ASPEED_CHARS_PER_GROUP_LABEL];
36*4b7f9568SRashmica Gupta } GPIOSetProperties;
37*4b7f9568SRashmica Gupta 
38*4b7f9568SRashmica Gupta enum GPIORegType {
39*4b7f9568SRashmica Gupta     gpio_not_a_reg,
40*4b7f9568SRashmica Gupta     gpio_reg_data_value,
41*4b7f9568SRashmica Gupta     gpio_reg_direction,
42*4b7f9568SRashmica Gupta     gpio_reg_int_enable,
43*4b7f9568SRashmica Gupta     gpio_reg_int_sens_0,
44*4b7f9568SRashmica Gupta     gpio_reg_int_sens_1,
45*4b7f9568SRashmica Gupta     gpio_reg_int_sens_2,
46*4b7f9568SRashmica Gupta     gpio_reg_int_status,
47*4b7f9568SRashmica Gupta     gpio_reg_reset_tolerant,
48*4b7f9568SRashmica Gupta     gpio_reg_debounce_1,
49*4b7f9568SRashmica Gupta     gpio_reg_debounce_2,
50*4b7f9568SRashmica Gupta     gpio_reg_cmd_source_0,
51*4b7f9568SRashmica Gupta     gpio_reg_cmd_source_1,
52*4b7f9568SRashmica Gupta     gpio_reg_data_read,
53*4b7f9568SRashmica Gupta     gpio_reg_input_mask,
54*4b7f9568SRashmica Gupta };
55*4b7f9568SRashmica Gupta 
56*4b7f9568SRashmica Gupta typedef struct AspeedGPIOReg {
57*4b7f9568SRashmica Gupta     uint16_t set_idx;
58*4b7f9568SRashmica Gupta     enum GPIORegType type;
59*4b7f9568SRashmica Gupta  } AspeedGPIOReg;
60*4b7f9568SRashmica Gupta 
61*4b7f9568SRashmica Gupta typedef struct  AspeedGPIOClass {
62*4b7f9568SRashmica Gupta     SysBusDevice parent_obj;
63*4b7f9568SRashmica Gupta     const GPIOSetProperties *props;
64*4b7f9568SRashmica Gupta     uint32_t nr_gpio_pins;
65*4b7f9568SRashmica Gupta     uint32_t nr_gpio_sets;
66*4b7f9568SRashmica Gupta     uint32_t gap;
67*4b7f9568SRashmica Gupta     const AspeedGPIOReg *reg_table;
68*4b7f9568SRashmica Gupta }  AspeedGPIOClass;
69*4b7f9568SRashmica Gupta 
70*4b7f9568SRashmica Gupta typedef struct AspeedGPIOState {
71*4b7f9568SRashmica Gupta     /* <private> */
72*4b7f9568SRashmica Gupta     SysBusDevice parent;
73*4b7f9568SRashmica Gupta 
74*4b7f9568SRashmica Gupta     /*< public >*/
75*4b7f9568SRashmica Gupta     MemoryRegion iomem;
76*4b7f9568SRashmica Gupta     int pending;
77*4b7f9568SRashmica Gupta     qemu_irq irq;
78*4b7f9568SRashmica Gupta     qemu_irq gpios[ASPEED_GPIO_NR_PINS];
79*4b7f9568SRashmica Gupta 
80*4b7f9568SRashmica Gupta /* Parallel GPIO Registers */
81*4b7f9568SRashmica Gupta     uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS];
82*4b7f9568SRashmica Gupta     struct GPIOSets {
83*4b7f9568SRashmica Gupta         uint32_t data_value; /* Reflects pin values */
84*4b7f9568SRashmica Gupta         uint32_t data_read; /* Contains last value written to data value */
85*4b7f9568SRashmica Gupta         uint32_t direction;
86*4b7f9568SRashmica Gupta         uint32_t int_enable;
87*4b7f9568SRashmica Gupta         uint32_t int_sens_0;
88*4b7f9568SRashmica Gupta         uint32_t int_sens_1;
89*4b7f9568SRashmica Gupta         uint32_t int_sens_2;
90*4b7f9568SRashmica Gupta         uint32_t int_status;
91*4b7f9568SRashmica Gupta         uint32_t reset_tol;
92*4b7f9568SRashmica Gupta         uint32_t cmd_source_0;
93*4b7f9568SRashmica Gupta         uint32_t cmd_source_1;
94*4b7f9568SRashmica Gupta         uint32_t debounce_1;
95*4b7f9568SRashmica Gupta         uint32_t debounce_2;
96*4b7f9568SRashmica Gupta         uint32_t input_mask;
97*4b7f9568SRashmica Gupta     } sets[ASPEED_GPIO_MAX_NR_SETS];
98*4b7f9568SRashmica Gupta } AspeedGPIOState;
99*4b7f9568SRashmica Gupta 
100*4b7f9568SRashmica Gupta #endif /* _ASPEED_GPIO_H_ */
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