xref: /qemu/include/hw/char/ibex_uart.h (revision a7d2d98c5944cec9ac8ed12215c2ea9d4545779b) 
1*a7d2d98cSAlistair Francis /*
2*a7d2d98cSAlistair Francis  * QEMU lowRISC Ibex UART device
3*a7d2d98cSAlistair Francis  *
4*a7d2d98cSAlistair Francis  * Copyright (c) 2020 Western Digital
5*a7d2d98cSAlistair Francis  *
6*a7d2d98cSAlistair Francis  * Permission is hereby granted, free of charge, to any person obtaining a copy
7*a7d2d98cSAlistair Francis  * of this software and associated documentation files (the "Software"), to deal
8*a7d2d98cSAlistair Francis  * in the Software without restriction, including without limitation the rights
9*a7d2d98cSAlistair Francis  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10*a7d2d98cSAlistair Francis  * copies of the Software, and to permit persons to whom the Software is
11*a7d2d98cSAlistair Francis  * furnished to do so, subject to the following conditions:
12*a7d2d98cSAlistair Francis  *
13*a7d2d98cSAlistair Francis  * The above copyright notice and this permission notice shall be included in
14*a7d2d98cSAlistair Francis  * all copies or substantial portions of the Software.
15*a7d2d98cSAlistair Francis  *
16*a7d2d98cSAlistair Francis  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17*a7d2d98cSAlistair Francis  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18*a7d2d98cSAlistair Francis  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19*a7d2d98cSAlistair Francis  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20*a7d2d98cSAlistair Francis  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21*a7d2d98cSAlistair Francis  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22*a7d2d98cSAlistair Francis  * THE SOFTWARE.
23*a7d2d98cSAlistair Francis  */
24*a7d2d98cSAlistair Francis 
25*a7d2d98cSAlistair Francis #ifndef HW_IBEX_UART_H
26*a7d2d98cSAlistair Francis #define HW_IBEX_UART_H
27*a7d2d98cSAlistair Francis 
28*a7d2d98cSAlistair Francis #include "hw/sysbus.h"
29*a7d2d98cSAlistair Francis #include "chardev/char-fe.h"
30*a7d2d98cSAlistair Francis #include "qemu/timer.h"
31*a7d2d98cSAlistair Francis 
32*a7d2d98cSAlistair Francis #define IBEX_UART_INTR_STATE   0x00
33*a7d2d98cSAlistair Francis     #define INTR_STATE_TX_WATERMARK (1 << 0)
34*a7d2d98cSAlistair Francis     #define INTR_STATE_RX_WATERMARK (1 << 1)
35*a7d2d98cSAlistair Francis     #define INTR_STATE_TX_EMPTY     (1 << 2)
36*a7d2d98cSAlistair Francis     #define INTR_STATE_RX_OVERFLOW  (1 << 3)
37*a7d2d98cSAlistair Francis #define IBEX_UART_INTR_ENABLE  0x04
38*a7d2d98cSAlistair Francis #define IBEX_UART_INTR_TEST    0x08
39*a7d2d98cSAlistair Francis 
40*a7d2d98cSAlistair Francis #define IBEX_UART_CTRL         0x0c
41*a7d2d98cSAlistair Francis     #define UART_CTRL_TX_ENABLE     (1 << 0)
42*a7d2d98cSAlistair Francis     #define UART_CTRL_RX_ENABLE     (1 << 1)
43*a7d2d98cSAlistair Francis     #define UART_CTRL_NF            (1 << 2)
44*a7d2d98cSAlistair Francis     #define UART_CTRL_SLPBK         (1 << 4)
45*a7d2d98cSAlistair Francis     #define UART_CTRL_LLPBK         (1 << 5)
46*a7d2d98cSAlistair Francis     #define UART_CTRL_PARITY_EN     (1 << 6)
47*a7d2d98cSAlistair Francis     #define UART_CTRL_PARITY_ODD    (1 << 7)
48*a7d2d98cSAlistair Francis     #define UART_CTRL_RXBLVL        (3 << 8)
49*a7d2d98cSAlistair Francis     #define UART_CTRL_NCO           (0xFFFF << 16)
50*a7d2d98cSAlistair Francis 
51*a7d2d98cSAlistair Francis #define IBEX_UART_STATUS       0x10
52*a7d2d98cSAlistair Francis     #define UART_STATUS_TXFULL  (1 << 0)
53*a7d2d98cSAlistair Francis     #define UART_STATUS_RXFULL  (1 << 1)
54*a7d2d98cSAlistair Francis     #define UART_STATUS_TXEMPTY (1 << 2)
55*a7d2d98cSAlistair Francis     #define UART_STATUS_RXIDLE  (1 << 4)
56*a7d2d98cSAlistair Francis     #define UART_STATUS_RXEMPTY (1 << 5)
57*a7d2d98cSAlistair Francis 
58*a7d2d98cSAlistair Francis #define IBEX_UART_RDATA        0x14
59*a7d2d98cSAlistair Francis #define IBEX_UART_WDATA        0x18
60*a7d2d98cSAlistair Francis 
61*a7d2d98cSAlistair Francis #define IBEX_UART_FIFO_CTRL    0x1c
62*a7d2d98cSAlistair Francis     #define FIFO_CTRL_RXRST          (1 << 0)
63*a7d2d98cSAlistair Francis     #define FIFO_CTRL_TXRST          (1 << 1)
64*a7d2d98cSAlistair Francis     #define FIFO_CTRL_RXILVL         (7 << 2)
65*a7d2d98cSAlistair Francis     #define FIFO_CTRL_RXILVL_SHIFT   (2)
66*a7d2d98cSAlistair Francis     #define FIFO_CTRL_TXILVL         (3 << 5)
67*a7d2d98cSAlistair Francis     #define FIFO_CTRL_TXILVL_SHIFT   (5)
68*a7d2d98cSAlistair Francis 
69*a7d2d98cSAlistair Francis #define IBEX_UART_FIFO_STATUS  0x20
70*a7d2d98cSAlistair Francis #define IBEX_UART_OVRD         0x24
71*a7d2d98cSAlistair Francis #define IBEX_UART_VAL          0x28
72*a7d2d98cSAlistair Francis #define IBEX_UART_TIMEOUT_CTRL 0x2c
73*a7d2d98cSAlistair Francis 
74*a7d2d98cSAlistair Francis #define IBEX_UART_TX_FIFO_SIZE 16
75*a7d2d98cSAlistair Francis 
76*a7d2d98cSAlistair Francis #define TYPE_IBEX_UART "ibex-uart"
77*a7d2d98cSAlistair Francis #define IBEX_UART(obj) \
78*a7d2d98cSAlistair Francis     OBJECT_CHECK(IbexUartState, (obj), TYPE_IBEX_UART)
79*a7d2d98cSAlistair Francis 
80*a7d2d98cSAlistair Francis typedef struct {
81*a7d2d98cSAlistair Francis     /* <private> */
82*a7d2d98cSAlistair Francis     SysBusDevice parent_obj;
83*a7d2d98cSAlistair Francis 
84*a7d2d98cSAlistair Francis     /* <public> */
85*a7d2d98cSAlistair Francis     MemoryRegion mmio;
86*a7d2d98cSAlistair Francis 
87*a7d2d98cSAlistair Francis     uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
88*a7d2d98cSAlistair Francis     uint32_t tx_level;
89*a7d2d98cSAlistair Francis 
90*a7d2d98cSAlistair Francis     QEMUTimer *fifo_trigger_handle;
91*a7d2d98cSAlistair Francis     uint64_t char_tx_time;
92*a7d2d98cSAlistair Francis 
93*a7d2d98cSAlistair Francis     uint32_t uart_intr_state;
94*a7d2d98cSAlistair Francis     uint32_t uart_intr_enable;
95*a7d2d98cSAlistair Francis     uint32_t uart_ctrl;
96*a7d2d98cSAlistair Francis     uint32_t uart_status;
97*a7d2d98cSAlistair Francis     uint32_t uart_rdata;
98*a7d2d98cSAlistair Francis     uint32_t uart_fifo_ctrl;
99*a7d2d98cSAlistair Francis     uint32_t uart_fifo_status;
100*a7d2d98cSAlistair Francis     uint32_t uart_ovrd;
101*a7d2d98cSAlistair Francis     uint32_t uart_val;
102*a7d2d98cSAlistair Francis     uint32_t uart_timeout_ctrl;
103*a7d2d98cSAlistair Francis 
104*a7d2d98cSAlistair Francis     CharBackend chr;
105*a7d2d98cSAlistair Francis     qemu_irq tx_watermark;
106*a7d2d98cSAlistair Francis     qemu_irq rx_watermark;
107*a7d2d98cSAlistair Francis     qemu_irq tx_empty;
108*a7d2d98cSAlistair Francis     qemu_irq rx_overflow;
109*a7d2d98cSAlistair Francis } IbexUartState;
110*a7d2d98cSAlistair Francis #endif /* HW_IBEX_UART_H */
111