1a7d2d98cSAlistair Francis /* 2a7d2d98cSAlistair Francis * QEMU lowRISC Ibex UART device 3a7d2d98cSAlistair Francis * 4a7d2d98cSAlistair Francis * Copyright (c) 2020 Western Digital 5a7d2d98cSAlistair Francis * 6a7d2d98cSAlistair Francis * Permission is hereby granted, free of charge, to any person obtaining a copy 7a7d2d98cSAlistair Francis * of this software and associated documentation files (the "Software"), to deal 8a7d2d98cSAlistair Francis * in the Software without restriction, including without limitation the rights 9a7d2d98cSAlistair Francis * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10a7d2d98cSAlistair Francis * copies of the Software, and to permit persons to whom the Software is 11a7d2d98cSAlistair Francis * furnished to do so, subject to the following conditions: 12a7d2d98cSAlistair Francis * 13a7d2d98cSAlistair Francis * The above copyright notice and this permission notice shall be included in 14a7d2d98cSAlistair Francis * all copies or substantial portions of the Software. 15a7d2d98cSAlistair Francis * 16a7d2d98cSAlistair Francis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17a7d2d98cSAlistair Francis * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18a7d2d98cSAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19a7d2d98cSAlistair Francis * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20a7d2d98cSAlistair Francis * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21a7d2d98cSAlistair Francis * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22a7d2d98cSAlistair Francis * THE SOFTWARE. 23a7d2d98cSAlistair Francis */ 24a7d2d98cSAlistair Francis 25a7d2d98cSAlistair Francis #ifndef HW_IBEX_UART_H 26a7d2d98cSAlistair Francis #define HW_IBEX_UART_H 27a7d2d98cSAlistair Francis 28a7d2d98cSAlistair Francis #include "hw/sysbus.h" 29a7d2d98cSAlistair Francis #include "chardev/char-fe.h" 30a7d2d98cSAlistair Francis #include "qemu/timer.h" 31a7d2d98cSAlistair Francis 32a7d2d98cSAlistair Francis #define IBEX_UART_INTR_STATE 0x00 33a7d2d98cSAlistair Francis #define INTR_STATE_TX_WATERMARK (1 << 0) 34a7d2d98cSAlistair Francis #define INTR_STATE_RX_WATERMARK (1 << 1) 35a7d2d98cSAlistair Francis #define INTR_STATE_TX_EMPTY (1 << 2) 36a7d2d98cSAlistair Francis #define INTR_STATE_RX_OVERFLOW (1 << 3) 37a7d2d98cSAlistair Francis #define IBEX_UART_INTR_ENABLE 0x04 38a7d2d98cSAlistair Francis #define IBEX_UART_INTR_TEST 0x08 39a7d2d98cSAlistair Francis 40a7d2d98cSAlistair Francis #define IBEX_UART_CTRL 0x0c 41a7d2d98cSAlistair Francis #define UART_CTRL_TX_ENABLE (1 << 0) 42a7d2d98cSAlistair Francis #define UART_CTRL_RX_ENABLE (1 << 1) 43a7d2d98cSAlistair Francis #define UART_CTRL_NF (1 << 2) 44a7d2d98cSAlistair Francis #define UART_CTRL_SLPBK (1 << 4) 45a7d2d98cSAlistair Francis #define UART_CTRL_LLPBK (1 << 5) 46a7d2d98cSAlistair Francis #define UART_CTRL_PARITY_EN (1 << 6) 47a7d2d98cSAlistair Francis #define UART_CTRL_PARITY_ODD (1 << 7) 48a7d2d98cSAlistair Francis #define UART_CTRL_RXBLVL (3 << 8) 49a7d2d98cSAlistair Francis #define UART_CTRL_NCO (0xFFFF << 16) 50a7d2d98cSAlistair Francis 51a7d2d98cSAlistair Francis #define IBEX_UART_STATUS 0x10 52a7d2d98cSAlistair Francis #define UART_STATUS_TXFULL (1 << 0) 53a7d2d98cSAlistair Francis #define UART_STATUS_RXFULL (1 << 1) 54a7d2d98cSAlistair Francis #define UART_STATUS_TXEMPTY (1 << 2) 55a7d2d98cSAlistair Francis #define UART_STATUS_RXIDLE (1 << 4) 56a7d2d98cSAlistair Francis #define UART_STATUS_RXEMPTY (1 << 5) 57a7d2d98cSAlistair Francis 58a7d2d98cSAlistair Francis #define IBEX_UART_RDATA 0x14 59a7d2d98cSAlistair Francis #define IBEX_UART_WDATA 0x18 60a7d2d98cSAlistair Francis 61a7d2d98cSAlistair Francis #define IBEX_UART_FIFO_CTRL 0x1c 62a7d2d98cSAlistair Francis #define FIFO_CTRL_RXRST (1 << 0) 63a7d2d98cSAlistair Francis #define FIFO_CTRL_TXRST (1 << 1) 64a7d2d98cSAlistair Francis #define FIFO_CTRL_RXILVL (7 << 2) 65a7d2d98cSAlistair Francis #define FIFO_CTRL_RXILVL_SHIFT (2) 66a7d2d98cSAlistair Francis #define FIFO_CTRL_TXILVL (3 << 5) 67a7d2d98cSAlistair Francis #define FIFO_CTRL_TXILVL_SHIFT (5) 68a7d2d98cSAlistair Francis 69a7d2d98cSAlistair Francis #define IBEX_UART_FIFO_STATUS 0x20 70a7d2d98cSAlistair Francis #define IBEX_UART_OVRD 0x24 71a7d2d98cSAlistair Francis #define IBEX_UART_VAL 0x28 72a7d2d98cSAlistair Francis #define IBEX_UART_TIMEOUT_CTRL 0x2c 73a7d2d98cSAlistair Francis 74a7d2d98cSAlistair Francis #define IBEX_UART_TX_FIFO_SIZE 16 75*940aabb9SAlistair Francis #define IBEX_UART_CLOCK 50000000 /* 50MHz clock */ 76a7d2d98cSAlistair Francis 77a7d2d98cSAlistair Francis #define TYPE_IBEX_UART "ibex-uart" 78a7d2d98cSAlistair Francis #define IBEX_UART(obj) \ 79a7d2d98cSAlistair Francis OBJECT_CHECK(IbexUartState, (obj), TYPE_IBEX_UART) 80a7d2d98cSAlistair Francis 81a7d2d98cSAlistair Francis typedef struct { 82a7d2d98cSAlistair Francis /* <private> */ 83a7d2d98cSAlistair Francis SysBusDevice parent_obj; 84a7d2d98cSAlistair Francis 85a7d2d98cSAlistair Francis /* <public> */ 86a7d2d98cSAlistair Francis MemoryRegion mmio; 87a7d2d98cSAlistair Francis 88a7d2d98cSAlistair Francis uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE]; 89a7d2d98cSAlistair Francis uint32_t tx_level; 90a7d2d98cSAlistair Francis 91a7d2d98cSAlistair Francis QEMUTimer *fifo_trigger_handle; 92a7d2d98cSAlistair Francis uint64_t char_tx_time; 93a7d2d98cSAlistair Francis 94a7d2d98cSAlistair Francis uint32_t uart_intr_state; 95a7d2d98cSAlistair Francis uint32_t uart_intr_enable; 96a7d2d98cSAlistair Francis uint32_t uart_ctrl; 97a7d2d98cSAlistair Francis uint32_t uart_status; 98a7d2d98cSAlistair Francis uint32_t uart_rdata; 99a7d2d98cSAlistair Francis uint32_t uart_fifo_ctrl; 100a7d2d98cSAlistair Francis uint32_t uart_fifo_status; 101a7d2d98cSAlistair Francis uint32_t uart_ovrd; 102a7d2d98cSAlistair Francis uint32_t uart_val; 103a7d2d98cSAlistair Francis uint32_t uart_timeout_ctrl; 104a7d2d98cSAlistair Francis 105*940aabb9SAlistair Francis Clock *f_clk; 106*940aabb9SAlistair Francis 107a7d2d98cSAlistair Francis CharBackend chr; 108a7d2d98cSAlistair Francis qemu_irq tx_watermark; 109a7d2d98cSAlistair Francis qemu_irq rx_watermark; 110a7d2d98cSAlistair Francis qemu_irq tx_empty; 111a7d2d98cSAlistair Francis qemu_irq rx_overflow; 112a7d2d98cSAlistair Francis } IbexUartState; 113a7d2d98cSAlistair Francis #endif /* HW_IBEX_UART_H */ 114