xref: /qemu/include/hw/char/cadence_uart.h (revision 4d43a603c71d0eb92534bc82b72933f329d8a64c)
18ae57b2fSPeter Crosthwaite /*
28ae57b2fSPeter Crosthwaite  * Device model for Cadence UART
38ae57b2fSPeter Crosthwaite  *
48ae57b2fSPeter Crosthwaite  * Copyright (c) 2010 Xilinx Inc.
58ae57b2fSPeter Crosthwaite  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
68ae57b2fSPeter Crosthwaite  * Copyright (c) 2012 PetaLogix Pty Ltd.
78ae57b2fSPeter Crosthwaite  * Written by Haibing Ma
88ae57b2fSPeter Crosthwaite  *            M.Habib
98ae57b2fSPeter Crosthwaite  *
108ae57b2fSPeter Crosthwaite  * This program is free software; you can redistribute it and/or
118ae57b2fSPeter Crosthwaite  * modify it under the terms of the GNU General Public License
128ae57b2fSPeter Crosthwaite  * as published by the Free Software Foundation; either version
138ae57b2fSPeter Crosthwaite  * 2 of the License, or (at your option) any later version.
148ae57b2fSPeter Crosthwaite  *
158ae57b2fSPeter Crosthwaite  * You should have received a copy of the GNU General Public License along
168ae57b2fSPeter Crosthwaite  * with this program; if not, see <http://www.gnu.org/licenses/>.
178ae57b2fSPeter Crosthwaite  */
188ae57b2fSPeter Crosthwaite 
198ae57b2fSPeter Crosthwaite #ifndef CADENCE_UART_H
208ae57b2fSPeter Crosthwaite 
218ae57b2fSPeter Crosthwaite #include "hw/sysbus.h"
22*4d43a603SMarc-André Lureau #include "chardev/char-fe.h"
238ae57b2fSPeter Crosthwaite #include "qemu/timer.h"
248ae57b2fSPeter Crosthwaite 
258ae57b2fSPeter Crosthwaite #define CADENCE_UART_RX_FIFO_SIZE           16
268ae57b2fSPeter Crosthwaite #define CADENCE_UART_TX_FIFO_SIZE           16
278ae57b2fSPeter Crosthwaite 
288ae57b2fSPeter Crosthwaite #define CADENCE_UART_R_MAX (0x48/4)
298ae57b2fSPeter Crosthwaite 
308ae57b2fSPeter Crosthwaite #define TYPE_CADENCE_UART "cadence_uart"
318ae57b2fSPeter Crosthwaite #define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
328ae57b2fSPeter Crosthwaite                                        TYPE_CADENCE_UART)
338ae57b2fSPeter Crosthwaite 
348ae57b2fSPeter Crosthwaite typedef struct {
358ae57b2fSPeter Crosthwaite     /*< private >*/
368ae57b2fSPeter Crosthwaite     SysBusDevice parent_obj;
378ae57b2fSPeter Crosthwaite 
388ae57b2fSPeter Crosthwaite     /*< public >*/
398ae57b2fSPeter Crosthwaite     MemoryRegion iomem;
408ae57b2fSPeter Crosthwaite     uint32_t r[CADENCE_UART_R_MAX];
418ae57b2fSPeter Crosthwaite     uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
428ae57b2fSPeter Crosthwaite     uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
438ae57b2fSPeter Crosthwaite     uint32_t rx_wpos;
448ae57b2fSPeter Crosthwaite     uint32_t rx_count;
458ae57b2fSPeter Crosthwaite     uint32_t tx_count;
468ae57b2fSPeter Crosthwaite     uint64_t char_tx_time;
47becdfa00SMarc-André Lureau     CharBackend chr;
488ae57b2fSPeter Crosthwaite     qemu_irq irq;
498ae57b2fSPeter Crosthwaite     QEMUTimer *fifo_trigger_handle;
508ae57b2fSPeter Crosthwaite } CadenceUARTState;
518ae57b2fSPeter Crosthwaite 
524be12ea0Sxiaoqiang zhao static inline DeviceState *cadence_uart_create(hwaddr addr,
534be12ea0Sxiaoqiang zhao                                         qemu_irq irq,
540ec7b3e7SMarc-André Lureau                                         Chardev *chr)
554be12ea0Sxiaoqiang zhao {
564be12ea0Sxiaoqiang zhao     DeviceState *dev;
574be12ea0Sxiaoqiang zhao     SysBusDevice *s;
584be12ea0Sxiaoqiang zhao 
594be12ea0Sxiaoqiang zhao     dev = qdev_create(NULL, TYPE_CADENCE_UART);
604be12ea0Sxiaoqiang zhao     s = SYS_BUS_DEVICE(dev);
614be12ea0Sxiaoqiang zhao     qdev_prop_set_chr(dev, "chardev", chr);
624be12ea0Sxiaoqiang zhao     qdev_init_nofail(dev);
634be12ea0Sxiaoqiang zhao     sysbus_mmio_map(s, 0, addr);
644be12ea0Sxiaoqiang zhao     sysbus_connect_irq(s, 0, irq);
654be12ea0Sxiaoqiang zhao 
664be12ea0Sxiaoqiang zhao     return dev;
674be12ea0Sxiaoqiang zhao }
684be12ea0Sxiaoqiang zhao 
698ae57b2fSPeter Crosthwaite #define CADENCE_UART_H
708ae57b2fSPeter Crosthwaite #endif
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