1cb9c377fSPaolo Bonzini #ifndef HW_FLASH_H 2175de524SMarkus Armbruster #define HW_FLASH_H 3cb9c377fSPaolo Bonzini 487ecb68bSpbrook /* NOR flash devices */ 5cfe5f011SAvi Kivity 6d4842052SMarkus Armbruster #include "exec/hwaddr.h" 7*db1015e9SEduardo Habkost #include "qom/object.h" 8cfe5f011SAvi Kivity 988eeee0aSbalrog /* pflash_cfi01.c */ 1016434065SMarkus Armbruster 11e7b62741SMarkus Armbruster #define TYPE_PFLASH_CFI01 "cfi.pflash01" 12*db1015e9SEduardo Habkost typedef struct PFlashCFI01 PFlashCFI01; 1381c7db72SMarkus Armbruster #define PFLASH_CFI01(obj) \ 1481c7db72SMarkus Armbruster OBJECT_CHECK(PFlashCFI01, (obj), TYPE_PFLASH_CFI01) 1516434065SMarkus Armbruster 1616434065SMarkus Armbruster 1716434065SMarkus Armbruster PFlashCFI01 *pflash_cfi01_register(hwaddr base, 18940d5b13SMarkus Armbruster const char *name, 19a8170e5eSAvi Kivity hwaddr size, 204be74634SMarkus Armbruster BlockBackend *blk, 21ce14710fSMarkus Armbruster uint32_t sector_len, 2216434065SMarkus Armbruster int width, 2387ecb68bSpbrook uint16_t id0, uint16_t id1, 246725070dSbalrog uint16_t id2, uint16_t id3, 2501e0451aSAnthony Liguori int be); 26e60cf765SPhilippe Mathieu-Daudé BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl); 2716434065SMarkus Armbruster MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl); 282d731dbdSMarkus Armbruster void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo *dinfo); 2987ecb68bSpbrook 3016434065SMarkus Armbruster /* pflash_cfi02.c */ 3116434065SMarkus Armbruster 32e7b62741SMarkus Armbruster #define TYPE_PFLASH_CFI02 "cfi.pflash02" 33*db1015e9SEduardo Habkost typedef struct PFlashCFI02 PFlashCFI02; 3481c7db72SMarkus Armbruster #define PFLASH_CFI02(obj) \ 3581c7db72SMarkus Armbruster OBJECT_CHECK(PFlashCFI02, (obj), TYPE_PFLASH_CFI02) 3616434065SMarkus Armbruster 3716434065SMarkus Armbruster 3816434065SMarkus Armbruster PFlashCFI02 *pflash_cfi02_register(hwaddr base, 39940d5b13SMarkus Armbruster const char *name, 4016434065SMarkus Armbruster hwaddr size, 4116434065SMarkus Armbruster BlockBackend *blk, 42ce14710fSMarkus Armbruster uint32_t sector_len, 4316434065SMarkus Armbruster int nb_mappings, 4416434065SMarkus Armbruster int width, 4516434065SMarkus Armbruster uint16_t id0, uint16_t id1, 4616434065SMarkus Armbruster uint16_t id2, uint16_t id3, 4716434065SMarkus Armbruster uint16_t unlock_addr0, 4816434065SMarkus Armbruster uint16_t unlock_addr1, 4916434065SMarkus Armbruster int be); 50cfe5f011SAvi Kivity 5187ecb68bSpbrook /* nand.c */ 524be74634SMarkus Armbruster DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id); 53d4220389SJuha Riihimäki void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale, 5451db57f7SJuan Quintela uint8_t ce, uint8_t wp, uint8_t gnd); 55d4220389SJuha Riihimäki void nand_getpins(DeviceState *dev, int *rb); 56d4220389SJuha Riihimäki void nand_setio(DeviceState *dev, uint32_t value); 57d4220389SJuha Riihimäki uint32_t nand_getio(DeviceState *dev); 58d4220389SJuha Riihimäki uint32_t nand_getbuswidth(DeviceState *dev); 5987ecb68bSpbrook 6087ecb68bSpbrook #define NAND_MFR_TOSHIBA 0x98 6187ecb68bSpbrook #define NAND_MFR_SAMSUNG 0xec 6287ecb68bSpbrook #define NAND_MFR_FUJITSU 0x04 6387ecb68bSpbrook #define NAND_MFR_NATIONAL 0x8f 6487ecb68bSpbrook #define NAND_MFR_RENESAS 0x07 6587ecb68bSpbrook #define NAND_MFR_STMICRO 0x20 6687ecb68bSpbrook #define NAND_MFR_HYNIX 0xad 6787ecb68bSpbrook #define NAND_MFR_MICRON 0x2c 6887ecb68bSpbrook 697e7c5e4cSbalrog /* onenand.c */ 70500954e3SJuha Riihimäki void *onenand_raw_otp(DeviceState *onenand_device); 717e7c5e4cSbalrog 7287ecb68bSpbrook /* ecc.c */ 73bc24a225SPaul Brook typedef struct { 7487ecb68bSpbrook uint8_t cp; /* Column parity */ 7587ecb68bSpbrook uint16_t lp[2]; /* Line parity */ 7687ecb68bSpbrook uint16_t count; 77bc24a225SPaul Brook } ECCState; 7887ecb68bSpbrook 79bc24a225SPaul Brook uint8_t ecc_digest(ECCState *s, uint8_t sample); 80bc24a225SPaul Brook void ecc_reset(ECCState *s); 8134f9f0b5SDmitry Eremin-Solenikov extern VMStateDescription vmstate_ecc_state; 82cb9c377fSPaolo Bonzini 83cb9c377fSPaolo Bonzini #endif 84