1cb9c377fSPaolo Bonzini #ifndef HW_FLASH_H 2cb9c377fSPaolo Bonzini #define HW_FLASH_H 1 3cb9c377fSPaolo Bonzini 487ecb68bSpbrook /* NOR flash devices */ 5cfe5f011SAvi Kivity 6022c62cbSPaolo Bonzini #include "exec/memory.h" 7cfe5f011SAvi Kivity 8c227f099SAnthony Liguori typedef struct pflash_t pflash_t; 987ecb68bSpbrook 1088eeee0aSbalrog /* pflash_cfi01.c */ 11a8170e5eSAvi Kivity pflash_t *pflash_cfi01_register(hwaddr base, 12cfe5f011SAvi Kivity DeviceState *qdev, const char *name, 13a8170e5eSAvi Kivity hwaddr size, 14*4be74634SMarkus Armbruster BlockBackend *blk, 1588eeee0aSbalrog uint32_t sector_len, int nb_blocs, int width, 1688eeee0aSbalrog uint16_t id0, uint16_t id1, 1701e0451aSAnthony Liguori uint16_t id2, uint16_t id3, int be); 1888eeee0aSbalrog 1988eeee0aSbalrog /* pflash_cfi02.c */ 20a8170e5eSAvi Kivity pflash_t *pflash_cfi02_register(hwaddr base, 21cfe5f011SAvi Kivity DeviceState *qdev, const char *name, 22a8170e5eSAvi Kivity hwaddr size, 23*4be74634SMarkus Armbruster BlockBackend *blk, uint32_t sector_len, 244fbd24baSbalrog int nb_blocs, int nb_mappings, int width, 2587ecb68bSpbrook uint16_t id0, uint16_t id1, 266725070dSbalrog uint16_t id2, uint16_t id3, 2701e0451aSAnthony Liguori uint16_t unlock_addr0, uint16_t unlock_addr1, 2801e0451aSAnthony Liguori int be); 2987ecb68bSpbrook 30cfe5f011SAvi Kivity MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl); 31cfe5f011SAvi Kivity 3287ecb68bSpbrook /* nand.c */ 33*4be74634SMarkus Armbruster DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id); 34d4220389SJuha Riihimäki void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale, 3551db57f7SJuan Quintela uint8_t ce, uint8_t wp, uint8_t gnd); 36d4220389SJuha Riihimäki void nand_getpins(DeviceState *dev, int *rb); 37d4220389SJuha Riihimäki void nand_setio(DeviceState *dev, uint32_t value); 38d4220389SJuha Riihimäki uint32_t nand_getio(DeviceState *dev); 39d4220389SJuha Riihimäki uint32_t nand_getbuswidth(DeviceState *dev); 4087ecb68bSpbrook 4187ecb68bSpbrook #define NAND_MFR_TOSHIBA 0x98 4287ecb68bSpbrook #define NAND_MFR_SAMSUNG 0xec 4387ecb68bSpbrook #define NAND_MFR_FUJITSU 0x04 4487ecb68bSpbrook #define NAND_MFR_NATIONAL 0x8f 4587ecb68bSpbrook #define NAND_MFR_RENESAS 0x07 4687ecb68bSpbrook #define NAND_MFR_STMICRO 0x20 4787ecb68bSpbrook #define NAND_MFR_HYNIX 0xad 4887ecb68bSpbrook #define NAND_MFR_MICRON 0x2c 4987ecb68bSpbrook 507e7c5e4cSbalrog /* onenand.c */ 51500954e3SJuha Riihimäki void *onenand_raw_otp(DeviceState *onenand_device); 527e7c5e4cSbalrog 5387ecb68bSpbrook /* ecc.c */ 54bc24a225SPaul Brook typedef struct { 5587ecb68bSpbrook uint8_t cp; /* Column parity */ 5687ecb68bSpbrook uint16_t lp[2]; /* Line parity */ 5787ecb68bSpbrook uint16_t count; 58bc24a225SPaul Brook } ECCState; 5987ecb68bSpbrook 60bc24a225SPaul Brook uint8_t ecc_digest(ECCState *s, uint8_t sample); 61bc24a225SPaul Brook void ecc_reset(ECCState *s); 6234f9f0b5SDmitry Eremin-Solenikov extern VMStateDescription vmstate_ecc_state; 63cb9c377fSPaolo Bonzini 64cb9c377fSPaolo Bonzini #endif 65