1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #ifndef XLNX_ZYNQMP_H 19 20 #include "qemu-common.h" 21 #include "hw/arm/arm.h" 22 #include "hw/intc/arm_gic.h" 23 #include "hw/net/cadence_gem.h" 24 #include "hw/char/cadence_uart.h" 25 26 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" 27 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ 28 TYPE_XLNX_ZYNQMP) 29 30 #define XLNX_ZYNQMP_NUM_APU_CPUS 4 31 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 32 #define XLNX_ZYNQMP_NUM_GEMS 4 33 #define XLNX_ZYNQMP_NUM_UARTS 2 34 35 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 36 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 37 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 38 39 #define XLNX_ZYNQMP_GIC_REGIONS 2 40 41 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets 42 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k 43 * aligned address in the 64k region. To implement each GIC region needs a 44 * number of memory region aliases. 45 */ 46 47 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x4000 48 #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1) 49 50 typedef struct XlnxZynqMPState { 51 /*< private >*/ 52 DeviceState parent_obj; 53 54 /*< public >*/ 55 ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; 56 ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; 57 GICState gic; 58 MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; 59 MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; 60 61 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; 62 CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; 63 64 char *boot_cpu; 65 ARMCPU *boot_cpu_ptr; 66 } XlnxZynqMPState; 67 68 #define XLNX_ZYNQMP_H 69 #endif 70