1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #ifndef XLNX_ZYNQMP_H 19 20 #include "qemu-common.h" 21 #include "hw/arm/arm.h" 22 #include "hw/intc/arm_gic.h" 23 #include "hw/net/cadence_gem.h" 24 25 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" 26 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ 27 TYPE_XLNX_ZYNQMP) 28 29 #define XLNX_ZYNQMP_NUM_CPUS 4 30 #define XLNX_ZYNQMP_NUM_GEMS 4 31 32 #define XLNX_ZYNQMP_GIC_REGIONS 2 33 34 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets 35 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k 36 * aligned address in the 64k region. To implement each GIC region needs a 37 * number of memory region aliases. 38 */ 39 40 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x4000 41 #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1) 42 43 typedef struct XlnxZynqMPState { 44 /*< private >*/ 45 DeviceState parent_obj; 46 47 /*< public >*/ 48 ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS]; 49 GICState gic; 50 MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; 51 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; 52 } XlnxZynqMPState; 53 54 #define XLNX_ZYNQMP_H 55 #endif 56