xref: /qemu/include/hw/arm/stm32f405_soc.h (revision 529fc5fd3e18ace8f739afd02dc0953354f39442)
1*529fc5fdSAlistair Francis /*
2*529fc5fdSAlistair Francis  * STM32F405 SoC
3*529fc5fdSAlistair Francis  *
4*529fc5fdSAlistair Francis  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5*529fc5fdSAlistair Francis  *
6*529fc5fdSAlistair Francis  * Permission is hereby granted, free of charge, to any person obtaining a copy
7*529fc5fdSAlistair Francis  * of this software and associated documentation files (the "Software"), to deal
8*529fc5fdSAlistair Francis  * in the Software without restriction, including without limitation the rights
9*529fc5fdSAlistair Francis  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10*529fc5fdSAlistair Francis  * copies of the Software, and to permit persons to whom the Software is
11*529fc5fdSAlistair Francis  * furnished to do so, subject to the following conditions:
12*529fc5fdSAlistair Francis  *
13*529fc5fdSAlistair Francis  * The above copyright notice and this permission notice shall be included in
14*529fc5fdSAlistair Francis  * all copies or substantial portions of the Software.
15*529fc5fdSAlistair Francis  *
16*529fc5fdSAlistair Francis  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17*529fc5fdSAlistair Francis  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18*529fc5fdSAlistair Francis  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19*529fc5fdSAlistair Francis  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20*529fc5fdSAlistair Francis  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21*529fc5fdSAlistair Francis  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22*529fc5fdSAlistair Francis  * THE SOFTWARE.
23*529fc5fdSAlistair Francis  */
24*529fc5fdSAlistair Francis 
25*529fc5fdSAlistair Francis #ifndef HW_ARM_STM32F405_SOC_H
26*529fc5fdSAlistair Francis #define HW_ARM_STM32F405_SOC_H
27*529fc5fdSAlistair Francis 
28*529fc5fdSAlistair Francis #include "hw/misc/stm32f4xx_syscfg.h"
29*529fc5fdSAlistair Francis #include "hw/timer/stm32f2xx_timer.h"
30*529fc5fdSAlistair Francis #include "hw/char/stm32f2xx_usart.h"
31*529fc5fdSAlistair Francis #include "hw/adc/stm32f2xx_adc.h"
32*529fc5fdSAlistair Francis #include "hw/misc/stm32f4xx_exti.h"
33*529fc5fdSAlistair Francis #include "hw/or-irq.h"
34*529fc5fdSAlistair Francis #include "hw/ssi/stm32f2xx_spi.h"
35*529fc5fdSAlistair Francis #include "hw/arm/armv7m.h"
36*529fc5fdSAlistair Francis 
37*529fc5fdSAlistair Francis #define TYPE_STM32F405_SOC "stm32f405-soc"
38*529fc5fdSAlistair Francis #define STM32F405_SOC(obj) \
39*529fc5fdSAlistair Francis     OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC)
40*529fc5fdSAlistair Francis 
41*529fc5fdSAlistair Francis #define STM_NUM_USARTS 7
42*529fc5fdSAlistair Francis #define STM_NUM_TIMERS 4
43*529fc5fdSAlistair Francis #define STM_NUM_ADCS 6
44*529fc5fdSAlistair Francis #define STM_NUM_SPIS 6
45*529fc5fdSAlistair Francis 
46*529fc5fdSAlistair Francis #define FLASH_BASE_ADDRESS 0x08000000
47*529fc5fdSAlistair Francis #define FLASH_SIZE (1024 * 1024)
48*529fc5fdSAlistair Francis #define SRAM_BASE_ADDRESS 0x20000000
49*529fc5fdSAlistair Francis #define SRAM_SIZE (192 * 1024)
50*529fc5fdSAlistair Francis 
51*529fc5fdSAlistair Francis typedef struct STM32F405State {
52*529fc5fdSAlistair Francis     /*< private >*/
53*529fc5fdSAlistair Francis     SysBusDevice parent_obj;
54*529fc5fdSAlistair Francis     /*< public >*/
55*529fc5fdSAlistair Francis 
56*529fc5fdSAlistair Francis     char *cpu_type;
57*529fc5fdSAlistair Francis 
58*529fc5fdSAlistair Francis     ARMv7MState armv7m;
59*529fc5fdSAlistair Francis 
60*529fc5fdSAlistair Francis     STM32F4xxSyscfgState syscfg;
61*529fc5fdSAlistair Francis     STM32F4xxExtiState exti;
62*529fc5fdSAlistair Francis     STM32F2XXUsartState usart[STM_NUM_USARTS];
63*529fc5fdSAlistair Francis     STM32F2XXTimerState timer[STM_NUM_TIMERS];
64*529fc5fdSAlistair Francis     qemu_or_irq adc_irqs;
65*529fc5fdSAlistair Francis     STM32F2XXADCState adc[STM_NUM_ADCS];
66*529fc5fdSAlistair Francis     STM32F2XXSPIState spi[STM_NUM_SPIS];
67*529fc5fdSAlistair Francis 
68*529fc5fdSAlistair Francis     MemoryRegion sram;
69*529fc5fdSAlistair Francis     MemoryRegion flash;
70*529fc5fdSAlistair Francis     MemoryRegion flash_alias;
71*529fc5fdSAlistair Francis } STM32F405State;
72*529fc5fdSAlistair Francis 
73*529fc5fdSAlistair Francis #endif
74