1 /* 2 * ARM SMMU Support 3 * 4 * Copyright (C) 2015-2016 Broadcom Corporation 5 * Copyright (c) 2017 Red Hat, Inc. 6 * Written by Prem Mallappa, Eric Auger 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef HW_ARM_SMMU_COMMON_H 20 #define HW_ARM_SMMU_COMMON_H 21 22 #include "hw/sysbus.h" 23 #include "hw/pci/pci.h" 24 #include "qom/object.h" 25 26 #define SMMU_PCI_BUS_MAX 256 27 #define SMMU_PCI_DEVFN_MAX 256 28 #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) 29 30 /* VMSAv8-64 Translation constants and functions */ 31 #define VMSA_LEVELS 4 32 #define VMSA_MAX_S2_CONCAT 16 33 34 #define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1) 35 #define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \ 36 (VMSA_LEVELS - (lvl))) 37 #define VMSA_IDXMSK(isz, strd, lvl) ((1ULL << \ 38 VMSA_BIT_LVL(isz, strd, lvl)) - 1) 39 40 /* 41 * Page table walk error types 42 */ 43 typedef enum { 44 SMMU_PTW_ERR_NONE, 45 SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */ 46 SMMU_PTW_ERR_TRANSLATION, /* Translation fault */ 47 SMMU_PTW_ERR_ADDR_SIZE, /* Address Size fault */ 48 SMMU_PTW_ERR_ACCESS, /* Access fault */ 49 SMMU_PTW_ERR_PERMISSION, /* Permission fault */ 50 } SMMUPTWEventType; 51 52 /* SMMU Stage */ 53 typedef enum { 54 SMMU_STAGE_1 = 1, 55 SMMU_STAGE_2, 56 SMMU_NESTED, 57 } SMMUStage; 58 59 typedef struct SMMUPTWEventInfo { 60 SMMUStage stage; 61 SMMUPTWEventType type; 62 dma_addr_t addr; /* fetched address that induced an abort, if any */ 63 } SMMUPTWEventInfo; 64 65 typedef struct SMMUTransTableInfo { 66 bool disabled; /* is the translation table disabled? */ 67 uint64_t ttb; /* TT base address */ 68 uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/ 69 uint8_t granule_sz; /* granule page shift */ 70 bool had; /* hierarchical attribute disable */ 71 } SMMUTransTableInfo; 72 73 typedef struct SMMUTLBEntry { 74 IOMMUTLBEntry entry; 75 uint8_t level; 76 uint8_t granule; 77 } SMMUTLBEntry; 78 79 /* Stage-2 configuration. */ 80 typedef struct SMMUS2Cfg { 81 uint8_t tsz; /* Size of IPA input region (S2T0SZ) */ 82 uint8_t sl0; /* Start level of translation (S2SL0) */ 83 bool affd; /* AF Fault Disable (S2AFFD) */ 84 bool record_faults; /* Record fault events (S2R) */ 85 uint8_t granule_sz; /* Granule page shift (based on S2TG) */ 86 uint8_t eff_ps; /* Effective PA output range (based on S2PS) */ 87 int vmid; /* Virtual Machine ID (S2VMID) */ 88 uint64_t vttb; /* Address of translation table base (S2TTB) */ 89 } SMMUS2Cfg; 90 91 /* 92 * Generic structure populated by derived SMMU devices 93 * after decoding the configuration information and used as 94 * input to the page table walk 95 */ 96 typedef struct SMMUTransCfg { 97 /* Shared fields between stage-1 and stage-2. */ 98 SMMUStage stage; /* translation stage */ 99 bool disabled; /* smmu is disabled */ 100 bool bypassed; /* translation is bypassed */ 101 bool aborted; /* translation is aborted */ 102 bool affd; /* AF fault disable */ 103 uint32_t iotlb_hits; /* counts IOTLB hits */ 104 uint32_t iotlb_misses; /* counts IOTLB misses*/ 105 /* Used by stage-1 only. */ 106 bool aa64; /* arch64 or aarch32 translation table */ 107 bool record_faults; /* record fault events */ 108 uint64_t ttb; /* TT base address */ 109 uint8_t oas; /* output address width */ 110 uint8_t tbi; /* Top Byte Ignore */ 111 int asid; 112 SMMUTransTableInfo tt[2]; 113 /* Used by stage-2 only. */ 114 struct SMMUS2Cfg s2cfg; 115 } SMMUTransCfg; 116 117 typedef struct SMMUDevice { 118 void *smmu; 119 PCIBus *bus; 120 int devfn; 121 IOMMUMemoryRegion iommu; 122 AddressSpace as; 123 uint32_t cfg_cache_hits; 124 uint32_t cfg_cache_misses; 125 QLIST_ENTRY(SMMUDevice) next; 126 } SMMUDevice; 127 128 typedef struct SMMUPciBus { 129 PCIBus *bus; 130 SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc */ 131 } SMMUPciBus; 132 133 typedef struct SMMUIOTLBKey { 134 uint64_t iova; 135 int asid; 136 int vmid; 137 uint8_t tg; 138 uint8_t level; 139 } SMMUIOTLBKey; 140 141 struct SMMUState { 142 /* <private> */ 143 SysBusDevice dev; 144 const char *mrtypename; 145 MemoryRegion iomem; 146 147 GHashTable *smmu_pcibus_by_busptr; 148 GHashTable *configs; /* cache for configuration data */ 149 GHashTable *iotlb; 150 SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX]; 151 PCIBus *pci_bus; 152 QLIST_HEAD(, SMMUDevice) devices_with_notifiers; 153 uint8_t bus_num; 154 PCIBus *primary_bus; 155 }; 156 157 struct SMMUBaseClass { 158 /* <private> */ 159 SysBusDeviceClass parent_class; 160 161 /*< public >*/ 162 163 DeviceRealize parent_realize; 164 165 }; 166 167 #define TYPE_ARM_SMMU "arm-smmu" 168 OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) 169 170 /* Return the SMMUPciBus handle associated to a PCI bus number */ 171 SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); 172 173 /* Return the stream ID of an SMMU device */ 174 static inline uint16_t smmu_get_sid(SMMUDevice *sdev) 175 { 176 return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); 177 } 178 179 /** 180 * smmu_ptw - Perform the page table walk for a given iova / access flags 181 * pair, according to @cfg translation config 182 */ 183 int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, 184 SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); 185 186 187 /* 188 * smmu_translate - Look for a translation in TLB, if not, do a PTW. 189 * Returns NULL on PTW error or incase of TLB permission errors. 190 */ 191 SMMUTLBEntry *smmu_translate(SMMUState *bs, SMMUTransCfg *cfg, dma_addr_t addr, 192 IOMMUAccessFlags flag, SMMUPTWEventInfo *info); 193 194 /** 195 * select_tt - compute which translation table shall be used according to 196 * the input iova and translation config and return the TT specific info 197 */ 198 SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova); 199 200 /* Return the SMMUDevice associated to @sid, or NULL if none */ 201 SMMUDevice *smmu_find_sdev(SMMUState *s, uint32_t sid); 202 203 #define SMMU_IOTLB_MAX_SIZE 256 204 205 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, 206 SMMUTransTableInfo *tt, hwaddr iova); 207 void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry); 208 SMMUIOTLBKey smmu_get_iotlb_key(int asid, int vmid, uint64_t iova, 209 uint8_t tg, uint8_t level); 210 void smmu_iotlb_inv_all(SMMUState *s); 211 void smmu_iotlb_inv_asid(SMMUState *s, int asid); 212 void smmu_iotlb_inv_vmid(SMMUState *s, int vmid); 213 void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, 214 uint8_t tg, uint64_t num_pages, uint8_t ttl); 215 216 /* Unmap the range of all the notifiers registered to any IOMMU mr */ 217 void smmu_inv_notifiers_all(SMMUState *s); 218 219 #endif /* HW_ARM_SMMU_COMMON_H */ 220