1 /* 2 * ARM SMMU Support 3 * 4 * Copyright (C) 2015-2016 Broadcom Corporation 5 * Copyright (c) 2017 Red Hat, Inc. 6 * Written by Prem Mallappa, Eric Auger 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef HW_ARM_SMMU_COMMON_H 20 #define HW_ARM_SMMU_COMMON_H 21 22 #include "hw/sysbus.h" 23 #include "hw/pci/pci.h" 24 25 #define SMMU_PCI_BUS_MAX 256 26 #define SMMU_PCI_DEVFN_MAX 256 27 #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) 28 29 #define SMMU_MAX_VA_BITS 48 30 31 /* 32 * Page table walk error types 33 */ 34 typedef enum { 35 SMMU_PTW_ERR_NONE, 36 SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */ 37 SMMU_PTW_ERR_TRANSLATION, /* Translation fault */ 38 SMMU_PTW_ERR_ADDR_SIZE, /* Address Size fault */ 39 SMMU_PTW_ERR_ACCESS, /* Access fault */ 40 SMMU_PTW_ERR_PERMISSION, /* Permission fault */ 41 } SMMUPTWEventType; 42 43 typedef struct SMMUPTWEventInfo { 44 SMMUPTWEventType type; 45 dma_addr_t addr; /* fetched address that induced an abort, if any */ 46 } SMMUPTWEventInfo; 47 48 typedef struct SMMUTransTableInfo { 49 bool disabled; /* is the translation table disabled? */ 50 uint64_t ttb; /* TT base address */ 51 uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/ 52 uint8_t granule_sz; /* granule page shift */ 53 } SMMUTransTableInfo; 54 55 typedef struct SMMUTLBEntry { 56 IOMMUTLBEntry entry; 57 uint8_t level; 58 uint8_t granule; 59 } SMMUTLBEntry; 60 61 /* 62 * Generic structure populated by derived SMMU devices 63 * after decoding the configuration information and used as 64 * input to the page table walk 65 */ 66 typedef struct SMMUTransCfg { 67 int stage; /* translation stage */ 68 bool aa64; /* arch64 or aarch32 translation table */ 69 bool disabled; /* smmu is disabled */ 70 bool bypassed; /* translation is bypassed */ 71 bool aborted; /* translation is aborted */ 72 uint64_t ttb; /* TT base address */ 73 uint8_t oas; /* output address width */ 74 uint8_t tbi; /* Top Byte Ignore */ 75 uint16_t asid; 76 SMMUTransTableInfo tt[2]; 77 uint32_t iotlb_hits; /* counts IOTLB hits for this asid */ 78 uint32_t iotlb_misses; /* counts IOTLB misses for this asid */ 79 } SMMUTransCfg; 80 81 typedef struct SMMUDevice { 82 void *smmu; 83 PCIBus *bus; 84 int devfn; 85 IOMMUMemoryRegion iommu; 86 AddressSpace as; 87 uint32_t cfg_cache_hits; 88 uint32_t cfg_cache_misses; 89 QLIST_ENTRY(SMMUDevice) next; 90 } SMMUDevice; 91 92 typedef struct SMMUPciBus { 93 PCIBus *bus; 94 SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc */ 95 } SMMUPciBus; 96 97 typedef struct SMMUIOTLBKey { 98 uint64_t iova; 99 uint16_t asid; 100 uint8_t tg; 101 uint8_t level; 102 } SMMUIOTLBKey; 103 104 typedef struct SMMUState { 105 /* <private> */ 106 SysBusDevice dev; 107 const char *mrtypename; 108 MemoryRegion iomem; 109 110 GHashTable *smmu_pcibus_by_busptr; 111 GHashTable *configs; /* cache for configuration data */ 112 GHashTable *iotlb; 113 SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX]; 114 PCIBus *pci_bus; 115 QLIST_HEAD(, SMMUDevice) devices_with_notifiers; 116 uint8_t bus_num; 117 PCIBus *primary_bus; 118 } SMMUState; 119 120 typedef struct { 121 /* <private> */ 122 SysBusDeviceClass parent_class; 123 124 /*< public >*/ 125 126 DeviceRealize parent_realize; 127 128 } SMMUBaseClass; 129 130 #define TYPE_ARM_SMMU "arm-smmu" 131 #define ARM_SMMU(obj) OBJECT_CHECK(SMMUState, (obj), TYPE_ARM_SMMU) 132 #define ARM_SMMU_CLASS(klass) \ 133 OBJECT_CLASS_CHECK(SMMUBaseClass, (klass), TYPE_ARM_SMMU) 134 #define ARM_SMMU_GET_CLASS(obj) \ 135 OBJECT_GET_CLASS(SMMUBaseClass, (obj), TYPE_ARM_SMMU) 136 137 /* Return the SMMUPciBus handle associated to a PCI bus number */ 138 SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); 139 140 /* Return the stream ID of an SMMU device */ 141 static inline uint16_t smmu_get_sid(SMMUDevice *sdev) 142 { 143 return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); 144 } 145 146 /** 147 * smmu_ptw - Perform the page table walk for a given iova / access flags 148 * pair, according to @cfg translation config 149 */ 150 int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, 151 SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); 152 153 /** 154 * select_tt - compute which translation table shall be used according to 155 * the input iova and translation config and return the TT specific info 156 */ 157 SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova); 158 159 /* Return the iommu mr associated to @sid, or NULL if none */ 160 IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid); 161 162 #define SMMU_IOTLB_MAX_SIZE 256 163 164 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, 165 SMMUTransTableInfo *tt, hwaddr iova); 166 void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry); 167 SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, 168 uint8_t tg, uint8_t level); 169 void smmu_iotlb_inv_all(SMMUState *s); 170 void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); 171 void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, 172 uint8_t tg, uint64_t num_pages, uint8_t ttl); 173 174 /* Unmap the range of all the notifiers registered to any IOMMU mr */ 175 void smmu_inv_notifiers_all(SMMUState *s); 176 177 /* Unmap the range of all the notifiers registered to @mr */ 178 void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr); 179 180 #endif /* HW_ARM_SMMU_COMMON_H */ 181