1 /* 2 * ARM SMMU Support 3 * 4 * Copyright (C) 2015-2016 Broadcom Corporation 5 * Copyright (c) 2017 Red Hat, Inc. 6 * Written by Prem Mallappa, Eric Auger 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef HW_ARM_SMMU_COMMON_H 20 #define HW_ARM_SMMU_COMMON_H 21 22 #include "hw/sysbus.h" 23 #include "hw/pci/pci.h" 24 #include "qom/object.h" 25 26 #define SMMU_PCI_BUS_MAX 256 27 #define SMMU_PCI_DEVFN_MAX 256 28 #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) 29 30 /* 31 * Page table walk error types 32 */ 33 typedef enum { 34 SMMU_PTW_ERR_NONE, 35 SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */ 36 SMMU_PTW_ERR_TRANSLATION, /* Translation fault */ 37 SMMU_PTW_ERR_ADDR_SIZE, /* Address Size fault */ 38 SMMU_PTW_ERR_ACCESS, /* Access fault */ 39 SMMU_PTW_ERR_PERMISSION, /* Permission fault */ 40 } SMMUPTWEventType; 41 42 typedef struct SMMUPTWEventInfo { 43 SMMUPTWEventType type; 44 dma_addr_t addr; /* fetched address that induced an abort, if any */ 45 } SMMUPTWEventInfo; 46 47 typedef struct SMMUTransTableInfo { 48 bool disabled; /* is the translation table disabled? */ 49 uint64_t ttb; /* TT base address */ 50 uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/ 51 uint8_t granule_sz; /* granule page shift */ 52 bool had; /* hierarchical attribute disable */ 53 } SMMUTransTableInfo; 54 55 typedef struct SMMUTLBEntry { 56 IOMMUTLBEntry entry; 57 uint8_t level; 58 uint8_t granule; 59 } SMMUTLBEntry; 60 61 /* Stage-2 configuration. */ 62 typedef struct SMMUS2Cfg { 63 uint8_t tsz; /* Size of IPA input region (S2T0SZ) */ 64 uint8_t sl0; /* Start level of translation (S2SL0) */ 65 bool affd; /* AF Fault Disable (S2AFFD) */ 66 bool record_faults; /* Record fault events (S2R) */ 67 uint8_t granule_sz; /* Granule page shift (based on S2TG) */ 68 uint8_t eff_ps; /* Effective PA output range (based on S2PS) */ 69 uint16_t vmid; /* Virtual Machine ID (S2VMID) */ 70 uint64_t vttb; /* Address of translation table base (S2TTB) */ 71 } SMMUS2Cfg; 72 73 /* 74 * Generic structure populated by derived SMMU devices 75 * after decoding the configuration information and used as 76 * input to the page table walk 77 */ 78 typedef struct SMMUTransCfg { 79 /* Shared fields between stage-1 and stage-2. */ 80 int stage; /* translation stage */ 81 bool disabled; /* smmu is disabled */ 82 bool bypassed; /* translation is bypassed */ 83 bool aborted; /* translation is aborted */ 84 uint32_t iotlb_hits; /* counts IOTLB hits */ 85 uint32_t iotlb_misses; /* counts IOTLB misses*/ 86 /* Used by stage-1 only. */ 87 bool aa64; /* arch64 or aarch32 translation table */ 88 bool record_faults; /* record fault events */ 89 uint64_t ttb; /* TT base address */ 90 uint8_t oas; /* output address width */ 91 uint8_t tbi; /* Top Byte Ignore */ 92 uint16_t asid; 93 SMMUTransTableInfo tt[2]; 94 /* Used by stage-2 only. */ 95 struct SMMUS2Cfg s2cfg; 96 } SMMUTransCfg; 97 98 typedef struct SMMUDevice { 99 void *smmu; 100 PCIBus *bus; 101 int devfn; 102 IOMMUMemoryRegion iommu; 103 AddressSpace as; 104 uint32_t cfg_cache_hits; 105 uint32_t cfg_cache_misses; 106 QLIST_ENTRY(SMMUDevice) next; 107 } SMMUDevice; 108 109 typedef struct SMMUPciBus { 110 PCIBus *bus; 111 SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc */ 112 } SMMUPciBus; 113 114 typedef struct SMMUIOTLBKey { 115 uint64_t iova; 116 uint16_t asid; 117 uint8_t tg; 118 uint8_t level; 119 } SMMUIOTLBKey; 120 121 struct SMMUState { 122 /* <private> */ 123 SysBusDevice dev; 124 const char *mrtypename; 125 MemoryRegion iomem; 126 127 GHashTable *smmu_pcibus_by_busptr; 128 GHashTable *configs; /* cache for configuration data */ 129 GHashTable *iotlb; 130 SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX]; 131 PCIBus *pci_bus; 132 QLIST_HEAD(, SMMUDevice) devices_with_notifiers; 133 uint8_t bus_num; 134 PCIBus *primary_bus; 135 }; 136 137 struct SMMUBaseClass { 138 /* <private> */ 139 SysBusDeviceClass parent_class; 140 141 /*< public >*/ 142 143 DeviceRealize parent_realize; 144 145 }; 146 147 #define TYPE_ARM_SMMU "arm-smmu" 148 OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) 149 150 /* Return the SMMUPciBus handle associated to a PCI bus number */ 151 SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); 152 153 /* Return the stream ID of an SMMU device */ 154 static inline uint16_t smmu_get_sid(SMMUDevice *sdev) 155 { 156 return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); 157 } 158 159 /** 160 * smmu_ptw - Perform the page table walk for a given iova / access flags 161 * pair, according to @cfg translation config 162 */ 163 int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, 164 SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); 165 166 /** 167 * select_tt - compute which translation table shall be used according to 168 * the input iova and translation config and return the TT specific info 169 */ 170 SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova); 171 172 /* Return the iommu mr associated to @sid, or NULL if none */ 173 IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid); 174 175 #define SMMU_IOTLB_MAX_SIZE 256 176 177 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, 178 SMMUTransTableInfo *tt, hwaddr iova); 179 void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry); 180 SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, 181 uint8_t tg, uint8_t level); 182 void smmu_iotlb_inv_all(SMMUState *s); 183 void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); 184 void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, 185 uint8_t tg, uint64_t num_pages, uint8_t ttl); 186 187 /* Unmap the range of all the notifiers registered to any IOMMU mr */ 188 void smmu_inv_notifiers_all(SMMUState *s); 189 190 #endif /* HW_ARM_SMMU_COMMON_H */ 191