1 /* 2 * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines 3 * 4 * These definitions are derived from those in Raspbian Linux at 5 * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h 6 * where they carry the following notice: 7 * 8 * Copyright (C) 2010 Broadcom 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program. If not, see <https://www.gnu.org/licenses/>. 22 * 23 * Various undocumented addresses and names come from Herman Hermitage's VC4 24 * documentation: 25 * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map 26 */ 27 28 #ifndef HW_ARM_RASPI_PLATFORM_H 29 #define HW_ARM_RASPI_PLATFORM_H 30 31 #include "hw/boards.h" 32 #include "hw/arm/boot.h" 33 34 #define TYPE_RASPI_BASE_MACHINE MACHINE_TYPE_NAME("raspi-base") 35 OBJECT_DECLARE_TYPE(RaspiBaseMachineState, RaspiBaseMachineClass, 36 RASPI_BASE_MACHINE) 37 38 struct RaspiBaseMachineState { 39 /*< private >*/ 40 MachineState parent_obj; 41 /*< public >*/ 42 struct arm_boot_info binfo; 43 }; 44 45 struct RaspiBaseMachineClass { 46 /*< private >*/ 47 MachineClass parent_obj; 48 /*< public >*/ 49 uint32_t board_rev; 50 }; 51 52 #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */ 53 #define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */ 54 #define INTE_OFFSET 0x2000 /* VC Interrupt controller */ 55 #define ST_OFFSET 0x3000 /* System Timer */ 56 #define TXP_OFFSET 0x4000 /* Transposer */ 57 #define JPEG_OFFSET 0x5000 58 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */ 59 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */ 60 #define ARBA_OFFSET 0x9000 61 #define BRDG_OFFSET 0xa000 62 #define ARM_OFFSET 0xB000 /* ARM control block */ 63 #define ARMCTRL_OFFSET (ARM_OFFSET + 0x000) 64 #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */ 65 #define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */ 66 #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores 67 * Doorbells & Mailboxes */ 68 #define PM_OFFSET 0x100000 /* Power Management */ 69 #define CPRMAN_OFFSET 0x101000 /* Clock Management */ 70 #define AVS_OFFSET 0x103000 /* Audio Video Standard */ 71 #define RNG_OFFSET 0x104000 72 #define GPIO_OFFSET 0x200000 73 #define UART0_OFFSET 0x201000 /* PL011 */ 74 #define MMCI0_OFFSET 0x202000 /* Legacy MMC */ 75 #define I2S_OFFSET 0x203000 /* PCM */ 76 #define SPI0_OFFSET 0x204000 /* SPI master */ 77 #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ 78 #define PIXV0_OFFSET 0x206000 79 #define PIXV1_OFFSET 0x207000 80 #define DPI_OFFSET 0x208000 81 #define DSI0_OFFSET 0x209000 /* Display Serial Interface */ 82 #define PWM_OFFSET 0x20c000 83 #define PERM_OFFSET 0x20d000 84 #define TEC_OFFSET 0x20e000 85 #define OTP_OFFSET 0x20f000 86 #define SLIM_OFFSET 0x210000 /* SLIMbus */ 87 #define CPG_OFFSET 0x211000 88 #define THERMAL_OFFSET 0x212000 89 #define AVSP_OFFSET 0x213000 90 #define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */ 91 #define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ 92 #define EMMC1_OFFSET 0x300000 93 #define EMMC2_OFFSET 0x340000 94 #define HVS_OFFSET 0x400000 95 #define SMI_OFFSET 0x600000 96 #define DSI1_OFFSET 0x700000 97 #define UCAM_OFFSET 0x800000 98 #define CMI_OFFSET 0x802000 99 #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ 100 #define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */ 101 #define VECA_OFFSET 0x806000 102 #define PIXV2_OFFSET 0x807000 103 #define HDMI_OFFSET 0x808000 104 #define HDCP_OFFSET 0x809000 105 #define ARBR0_OFFSET 0x80a000 106 #define DBUS_OFFSET 0x900000 107 #define AVE0_OFFSET 0x910000 108 #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ 109 #define V3D_OFFSET 0xc00000 110 #define SDRAMC_OFFSET 0xe00000 111 #define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */ 112 #define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */ 113 #define ARBR1_OFFSET 0xe04000 114 #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ 115 #define DCRC_OFFSET 0xe07000 116 #define AXIP_OFFSET 0xe08000 117 118 /* GPU interrupts */ 119 #define INTERRUPT_TIMER0 0 120 #define INTERRUPT_TIMER1 1 121 #define INTERRUPT_TIMER2 2 122 #define INTERRUPT_TIMER3 3 123 #define INTERRUPT_CODEC0 4 124 #define INTERRUPT_CODEC1 5 125 #define INTERRUPT_CODEC2 6 126 #define INTERRUPT_JPEG 7 127 #define INTERRUPT_ISP 8 128 #define INTERRUPT_USB 9 129 #define INTERRUPT_3D 10 130 #define INTERRUPT_TRANSPOSER 11 131 #define INTERRUPT_MULTICORESYNC0 12 132 #define INTERRUPT_MULTICORESYNC1 13 133 #define INTERRUPT_MULTICORESYNC2 14 134 #define INTERRUPT_MULTICORESYNC3 15 135 #define INTERRUPT_DMA0 16 136 #define INTERRUPT_DMA1 17 137 #define INTERRUPT_DMA2 18 138 #define INTERRUPT_DMA3 19 139 #define INTERRUPT_DMA4 20 140 #define INTERRUPT_DMA5 21 141 #define INTERRUPT_DMA6 22 142 #define INTERRUPT_DMA7 23 143 #define INTERRUPT_DMA8 24 144 #define INTERRUPT_DMA9 25 145 #define INTERRUPT_DMA10 26 146 #define INTERRUPT_DMA11 27 147 #define INTERRUPT_DMA12 28 148 #define INTERRUPT_AUX 29 149 #define INTERRUPT_ARM 30 150 #define INTERRUPT_VPUDMA 31 151 #define INTERRUPT_HOSTPORT 32 152 #define INTERRUPT_VIDEOSCALER 33 153 #define INTERRUPT_CCP2TX 34 154 #define INTERRUPT_SDC 35 155 #define INTERRUPT_DSI0 36 156 #define INTERRUPT_AVE 37 157 #define INTERRUPT_CAM0 38 158 #define INTERRUPT_CAM1 39 159 #define INTERRUPT_HDMI0 40 160 #define INTERRUPT_HDMI1 41 161 #define INTERRUPT_PIXELVALVE1 42 162 #define INTERRUPT_I2CSPISLV 43 163 #define INTERRUPT_DSI1 44 164 #define INTERRUPT_PWA0 45 165 #define INTERRUPT_PWA1 46 166 #define INTERRUPT_CPR 47 167 #define INTERRUPT_SMI 48 168 #define INTERRUPT_GPIO0 49 169 #define INTERRUPT_GPIO1 50 170 #define INTERRUPT_GPIO2 51 171 #define INTERRUPT_GPIO3 52 172 #define INTERRUPT_I2C 53 173 #define INTERRUPT_SPI 54 174 #define INTERRUPT_I2SPCM 55 175 #define INTERRUPT_SDIO 56 176 #define INTERRUPT_UART0 57 177 #define INTERRUPT_SLIMBUS 58 178 #define INTERRUPT_VEC 59 179 #define INTERRUPT_CPG 60 180 #define INTERRUPT_RNG 61 181 #define INTERRUPT_ARASANSDIO 62 182 #define INTERRUPT_AVSPMON 63 183 184 /* ARM CPU IRQs use a private number space */ 185 #define INTERRUPT_ARM_TIMER 0 186 #define INTERRUPT_ARM_MAILBOX 1 187 #define INTERRUPT_ARM_DOORBELL_0 2 188 #define INTERRUPT_ARM_DOORBELL_1 3 189 #define INTERRUPT_VPU0_HALTED 4 190 #define INTERRUPT_VPU1_HALTED 5 191 #define INTERRUPT_ILLEGAL_TYPE0 6 192 #define INTERRUPT_ILLEGAL_TYPE1 7 193 194 /* Clock rates */ 195 #define RPI_FIRMWARE_EMMC_CLK_RATE 50000000 196 #define RPI_FIRMWARE_UART_CLK_RATE 3000000 197 /* 198 * TODO: this is really SoC-specific; we might want to 199 * set it per-SoC if it turns out any guests care. 200 */ 201 #define RPI_FIRMWARE_CORE_CLK_RATE 350000000 202 #define RPI_FIRMWARE_DEFAULT_CLK_RATE 700000000 203 204 #endif 205