1 /* 2 * Texas Instruments OMAP processors. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HW_ARM_OMAP_H 21 #define HW_ARM_OMAP_H 22 23 #include "exec/memory.h" 24 #include "target/arm/cpu-qom.h" 25 #include "qemu/log.h" 26 #include "qom/object.h" 27 28 # define OMAP_EMIFS_BASE 0x00000000 29 # define OMAP2_Q0_BASE 0x00000000 30 # define OMAP_CS0_BASE 0x00000000 31 # define OMAP_CS1_BASE 0x04000000 32 # define OMAP_CS2_BASE 0x08000000 33 # define OMAP_CS3_BASE 0x0c000000 34 # define OMAP_EMIFF_BASE 0x10000000 35 # define OMAP_IMIF_BASE 0x20000000 36 # define OMAP_LOCALBUS_BASE 0x30000000 37 # define OMAP2_Q1_BASE 0x40000000 38 # define OMAP2_L4_BASE 0x48000000 39 # define OMAP2_SRAM_BASE 0x40200000 40 # define OMAP2_L3_BASE 0x68000000 41 # define OMAP2_Q2_BASE 0x80000000 42 # define OMAP2_Q3_BASE 0xc0000000 43 # define OMAP_MPUI_BASE 0xe1000000 44 45 # define OMAP730_SRAM_SIZE 0x00032000 46 # define OMAP15XX_SRAM_SIZE 0x00030000 47 # define OMAP16XX_SRAM_SIZE 0x00004000 48 # define OMAP1611_SRAM_SIZE 0x0003e800 49 # define OMAP242X_SRAM_SIZE 0x000a0000 50 # define OMAP243X_SRAM_SIZE 0x00010000 51 # define OMAP_CS0_SIZE 0x04000000 52 # define OMAP_CS1_SIZE 0x04000000 53 # define OMAP_CS2_SIZE 0x04000000 54 # define OMAP_CS3_SIZE 0x04000000 55 56 /* omap_clk.c */ 57 struct omap_mpu_state_s; 58 typedef struct clk *omap_clk; 59 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); 60 void omap_clk_init(struct omap_mpu_state_s *mpu); 61 void omap_clk_adduser(struct clk *clk, qemu_irq user); 62 void omap_clk_get(omap_clk clk); 63 void omap_clk_put(omap_clk clk); 64 void omap_clk_onoff(omap_clk clk, int on); 65 void omap_clk_canidle(omap_clk clk, int can); 66 void omap_clk_setrate(omap_clk clk, int divide, int multiply); 67 int64_t omap_clk_getrate(omap_clk clk); 68 void omap_clk_reparent(omap_clk clk, omap_clk parent); 69 70 /* omap_intc.c */ 71 #define TYPE_OMAP_INTC "common-omap-intc" 72 typedef struct OMAPIntcState OMAPIntcState; 73 DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC) 74 75 76 /* 77 * TODO: Ideally we should have a clock framework that 78 * let us wire these clocks up with QOM properties or links. 79 * 80 * qdev should support a generic means of defining a 'port' with 81 * an arbitrary interface for connecting two devices. Then we 82 * could reframe the omap clock API in terms of clock ports, 83 * and get some type safety. For now the best qdev provides is 84 * passing an arbitrary pointer. 85 * (It's not possible to pass in the string which is the clock 86 * name, because this device does not have the necessary information 87 * (ie the struct omap_mpu_state_s*) to do the clockname to pointer 88 * translation.) 89 */ 90 void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk); 91 void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk); 92 93 /* omap_i2c.c */ 94 #define TYPE_OMAP_I2C "omap_i2c" 95 OBJECT_DECLARE_SIMPLE_TYPE(OMAPI2CState, OMAP_I2C) 96 97 98 /* TODO: clock framework (see above) */ 99 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); 100 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); 101 102 /* omap_gpio.c */ 103 #define TYPE_OMAP1_GPIO "omap-gpio" 104 typedef struct Omap1GpioState Omap1GpioState; 105 DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO, 106 TYPE_OMAP1_GPIO) 107 108 #define TYPE_OMAP2_GPIO "omap2-gpio" 109 typedef struct Omap2GpioState Omap2GpioState; 110 DECLARE_INSTANCE_CHECKER(Omap2GpioState, OMAP2_GPIO, 111 TYPE_OMAP2_GPIO) 112 113 /* TODO: clock framework (see above) */ 114 void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk); 115 116 void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk); 117 void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk); 118 119 /* OMAP2 l4 Interconnect */ 120 struct omap_l4_s; 121 struct omap_l4_region_s { 122 hwaddr offset; 123 size_t size; 124 int access; 125 }; 126 struct omap_l4_agent_info_s { 127 int ta; 128 int region; 129 int regions; 130 int ta_region; 131 }; 132 struct omap_target_agent_s { 133 MemoryRegion iomem; 134 struct omap_l4_s *bus; 135 int regions; 136 const struct omap_l4_region_s *start; 137 hwaddr base; 138 uint32_t component; 139 uint32_t control; 140 uint32_t status; 141 }; 142 struct omap_l4_s *omap_l4_init(MemoryRegion *address_space, 143 hwaddr base, int ta_num); 144 145 struct omap_target_agent_s; 146 struct omap_target_agent_s *omap_l4ta_get( 147 struct omap_l4_s *bus, 148 const struct omap_l4_region_s *regions, 149 const struct omap_l4_agent_info_s *agents, 150 int cs); 151 hwaddr omap_l4_attach(struct omap_target_agent_s *ta, 152 int region, MemoryRegion *mr); 153 hwaddr omap_l4_region_base(struct omap_target_agent_s *ta, 154 int region); 155 hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, 156 int region); 157 158 /* OMAP2 SDRAM controller */ 159 struct omap_sdrc_s; 160 struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, 161 hwaddr base); 162 void omap_sdrc_reset(struct omap_sdrc_s *s); 163 164 /* OMAP2 general purpose memory controller */ 165 struct omap_gpmc_s; 166 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, 167 hwaddr base, 168 qemu_irq irq, qemu_irq drq); 169 void omap_gpmc_reset(struct omap_gpmc_s *s); 170 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); 171 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); 172 173 /* 174 * Common IRQ numbers for level 1 interrupt handler 175 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. 176 */ 177 # define OMAP_INT_CAMERA 1 178 # define OMAP_INT_FIQ 3 179 # define OMAP_INT_RTDX 6 180 # define OMAP_INT_DSP_MMU_ABORT 7 181 # define OMAP_INT_HOST 8 182 # define OMAP_INT_ABORT 9 183 # define OMAP_INT_BRIDGE_PRIV 13 184 # define OMAP_INT_GPIO_BANK1 14 185 # define OMAP_INT_UART3 15 186 # define OMAP_INT_TIMER3 16 187 # define OMAP_INT_DMA_CH0_6 19 188 # define OMAP_INT_DMA_CH1_7 20 189 # define OMAP_INT_DMA_CH2_8 21 190 # define OMAP_INT_DMA_CH3 22 191 # define OMAP_INT_DMA_CH4 23 192 # define OMAP_INT_DMA_CH5 24 193 # define OMAP_INT_DMA_LCD 25 194 # define OMAP_INT_TIMER1 26 195 # define OMAP_INT_WD_TIMER 27 196 # define OMAP_INT_BRIDGE_PUB 28 197 # define OMAP_INT_TIMER2 30 198 # define OMAP_INT_LCD_CTRL 31 199 200 /* 201 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler 202 */ 203 # define OMAP_INT_15XX_IH2_IRQ 0 204 # define OMAP_INT_15XX_LB_MMU 17 205 # define OMAP_INT_15XX_LOCAL_BUS 29 206 207 /* 208 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler 209 */ 210 # define OMAP_INT_1510_SPI_TX 4 211 # define OMAP_INT_1510_SPI_RX 5 212 # define OMAP_INT_1510_DSP_MAILBOX1 10 213 # define OMAP_INT_1510_DSP_MAILBOX2 11 214 215 /* 216 * OMAP-310 specific IRQ numbers for level 1 interrupt handler 217 */ 218 # define OMAP_INT_310_McBSP2_TX 4 219 # define OMAP_INT_310_McBSP2_RX 5 220 # define OMAP_INT_310_HSB_MAILBOX1 12 221 # define OMAP_INT_310_HSAB_MMU 18 222 223 /* 224 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler 225 */ 226 # define OMAP_INT_1610_IH2_IRQ 0 227 # define OMAP_INT_1610_IH2_FIQ 2 228 # define OMAP_INT_1610_McBSP2_TX 4 229 # define OMAP_INT_1610_McBSP2_RX 5 230 # define OMAP_INT_1610_DSP_MAILBOX1 10 231 # define OMAP_INT_1610_DSP_MAILBOX2 11 232 # define OMAP_INT_1610_LCD_LINE 12 233 # define OMAP_INT_1610_GPTIMER1 17 234 # define OMAP_INT_1610_GPTIMER2 18 235 # define OMAP_INT_1610_SSR_FIFO_0 29 236 237 /* 238 * OMAP-730 specific IRQ numbers for level 1 interrupt handler 239 */ 240 # define OMAP_INT_730_IH2_FIQ 0 241 # define OMAP_INT_730_IH2_IRQ 1 242 # define OMAP_INT_730_USB_NON_ISO 2 243 # define OMAP_INT_730_USB_ISO 3 244 # define OMAP_INT_730_ICR 4 245 # define OMAP_INT_730_EAC 5 246 # define OMAP_INT_730_GPIO_BANK1 6 247 # define OMAP_INT_730_GPIO_BANK2 7 248 # define OMAP_INT_730_GPIO_BANK3 8 249 # define OMAP_INT_730_McBSP2TX 10 250 # define OMAP_INT_730_McBSP2RX 11 251 # define OMAP_INT_730_McBSP2RX_OVF 12 252 # define OMAP_INT_730_LCD_LINE 14 253 # define OMAP_INT_730_GSM_PROTECT 15 254 # define OMAP_INT_730_TIMER3 16 255 # define OMAP_INT_730_GPIO_BANK5 17 256 # define OMAP_INT_730_GPIO_BANK6 18 257 # define OMAP_INT_730_SPGIO_WR 29 258 259 /* 260 * Common IRQ numbers for level 2 interrupt handler 261 */ 262 # define OMAP_INT_KEYBOARD 1 263 # define OMAP_INT_uWireTX 2 264 # define OMAP_INT_uWireRX 3 265 # define OMAP_INT_I2C 4 266 # define OMAP_INT_MPUIO 5 267 # define OMAP_INT_USB_HHC_1 6 268 # define OMAP_INT_McBSP3TX 10 269 # define OMAP_INT_McBSP3RX 11 270 # define OMAP_INT_McBSP1TX 12 271 # define OMAP_INT_McBSP1RX 13 272 # define OMAP_INT_UART1 14 273 # define OMAP_INT_UART2 15 274 # define OMAP_INT_USB_W2FC 20 275 # define OMAP_INT_1WIRE 21 276 # define OMAP_INT_OS_TIMER 22 277 # define OMAP_INT_OQN 23 278 # define OMAP_INT_GAUGE_32K 24 279 # define OMAP_INT_RTC_TIMER 25 280 # define OMAP_INT_RTC_ALARM 26 281 # define OMAP_INT_DSP_MMU 28 282 283 /* 284 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler 285 */ 286 # define OMAP_INT_1510_BT_MCSI1TX 16 287 # define OMAP_INT_1510_BT_MCSI1RX 17 288 # define OMAP_INT_1510_SoSSI_MATCH 19 289 # define OMAP_INT_1510_MEM_STICK 27 290 # define OMAP_INT_1510_COM_SPI_RO 31 291 292 /* 293 * OMAP-310 specific IRQ numbers for level 2 interrupt handler 294 */ 295 # define OMAP_INT_310_FAC 0 296 # define OMAP_INT_310_USB_HHC_2 7 297 # define OMAP_INT_310_MCSI1_FE 16 298 # define OMAP_INT_310_MCSI2_FE 17 299 # define OMAP_INT_310_USB_W2FC_ISO 29 300 # define OMAP_INT_310_USB_W2FC_NON_ISO 30 301 # define OMAP_INT_310_McBSP2RX_OF 31 302 303 /* 304 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler 305 */ 306 # define OMAP_INT_1610_FAC 0 307 # define OMAP_INT_1610_USB_HHC_2 7 308 # define OMAP_INT_1610_USB_OTG 8 309 # define OMAP_INT_1610_SoSSI 9 310 # define OMAP_INT_1610_BT_MCSI1TX 16 311 # define OMAP_INT_1610_BT_MCSI1RX 17 312 # define OMAP_INT_1610_SoSSI_MATCH 19 313 # define OMAP_INT_1610_MEM_STICK 27 314 # define OMAP_INT_1610_McBSP2RX_OF 31 315 # define OMAP_INT_1610_STI 32 316 # define OMAP_INT_1610_STI_WAKEUP 33 317 # define OMAP_INT_1610_GPTIMER3 34 318 # define OMAP_INT_1610_GPTIMER4 35 319 # define OMAP_INT_1610_GPTIMER5 36 320 # define OMAP_INT_1610_GPTIMER6 37 321 # define OMAP_INT_1610_GPTIMER7 38 322 # define OMAP_INT_1610_GPTIMER8 39 323 # define OMAP_INT_1610_GPIO_BANK2 40 324 # define OMAP_INT_1610_GPIO_BANK3 41 325 # define OMAP_INT_1610_MMC2 42 326 # define OMAP_INT_1610_CF 43 327 # define OMAP_INT_1610_WAKE_UP_REQ 46 328 # define OMAP_INT_1610_GPIO_BANK4 48 329 # define OMAP_INT_1610_SPI 49 330 # define OMAP_INT_1610_DMA_CH6 53 331 # define OMAP_INT_1610_DMA_CH7 54 332 # define OMAP_INT_1610_DMA_CH8 55 333 # define OMAP_INT_1610_DMA_CH9 56 334 # define OMAP_INT_1610_DMA_CH10 57 335 # define OMAP_INT_1610_DMA_CH11 58 336 # define OMAP_INT_1610_DMA_CH12 59 337 # define OMAP_INT_1610_DMA_CH13 60 338 # define OMAP_INT_1610_DMA_CH14 61 339 # define OMAP_INT_1610_DMA_CH15 62 340 # define OMAP_INT_1610_NAND 63 341 342 /* 343 * OMAP-730 specific IRQ numbers for level 2 interrupt handler 344 */ 345 # define OMAP_INT_730_HW_ERRORS 0 346 # define OMAP_INT_730_NFIQ_PWR_FAIL 1 347 # define OMAP_INT_730_CFCD 2 348 # define OMAP_INT_730_CFIREQ 3 349 # define OMAP_INT_730_I2C 4 350 # define OMAP_INT_730_PCC 5 351 # define OMAP_INT_730_MPU_EXT_NIRQ 6 352 # define OMAP_INT_730_SPI_100K_1 7 353 # define OMAP_INT_730_SYREN_SPI 8 354 # define OMAP_INT_730_VLYNQ 9 355 # define OMAP_INT_730_GPIO_BANK4 10 356 # define OMAP_INT_730_McBSP1TX 11 357 # define OMAP_INT_730_McBSP1RX 12 358 # define OMAP_INT_730_McBSP1RX_OF 13 359 # define OMAP_INT_730_UART_MODEM_IRDA_2 14 360 # define OMAP_INT_730_UART_MODEM_1 15 361 # define OMAP_INT_730_MCSI 16 362 # define OMAP_INT_730_uWireTX 17 363 # define OMAP_INT_730_uWireRX 18 364 # define OMAP_INT_730_SMC_CD 19 365 # define OMAP_INT_730_SMC_IREQ 20 366 # define OMAP_INT_730_HDQ_1WIRE 21 367 # define OMAP_INT_730_TIMER32K 22 368 # define OMAP_INT_730_MMC_SDIO 23 369 # define OMAP_INT_730_UPLD 24 370 # define OMAP_INT_730_USB_HHC_1 27 371 # define OMAP_INT_730_USB_HHC_2 28 372 # define OMAP_INT_730_USB_GENI 29 373 # define OMAP_INT_730_USB_OTG 30 374 # define OMAP_INT_730_CAMERA_IF 31 375 # define OMAP_INT_730_RNG 32 376 # define OMAP_INT_730_DUAL_MODE_TIMER 33 377 # define OMAP_INT_730_DBB_RF_EN 34 378 # define OMAP_INT_730_MPUIO_KEYPAD 35 379 # define OMAP_INT_730_SHA1_MD5 36 380 # define OMAP_INT_730_SPI_100K_2 37 381 # define OMAP_INT_730_RNG_IDLE 38 382 # define OMAP_INT_730_MPUIO 39 383 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 384 # define OMAP_INT_730_LLPC_OE_FALLING 41 385 # define OMAP_INT_730_LLPC_OE_RISING 42 386 # define OMAP_INT_730_LLPC_VSYNC 43 387 # define OMAP_INT_730_WAKE_UP_REQ 46 388 # define OMAP_INT_730_DMA_CH6 53 389 # define OMAP_INT_730_DMA_CH7 54 390 # define OMAP_INT_730_DMA_CH8 55 391 # define OMAP_INT_730_DMA_CH9 56 392 # define OMAP_INT_730_DMA_CH10 57 393 # define OMAP_INT_730_DMA_CH11 58 394 # define OMAP_INT_730_DMA_CH12 59 395 # define OMAP_INT_730_DMA_CH13 60 396 # define OMAP_INT_730_DMA_CH14 61 397 # define OMAP_INT_730_DMA_CH15 62 398 # define OMAP_INT_730_NAND 63 399 400 /* 401 * OMAP-24xx common IRQ numbers 402 */ 403 # define OMAP_INT_24XX_STI 4 404 # define OMAP_INT_24XX_SYS_NIRQ 7 405 # define OMAP_INT_24XX_L3_IRQ 10 406 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 407 # define OMAP_INT_24XX_SDMA_IRQ0 12 408 # define OMAP_INT_24XX_SDMA_IRQ1 13 409 # define OMAP_INT_24XX_SDMA_IRQ2 14 410 # define OMAP_INT_24XX_SDMA_IRQ3 15 411 # define OMAP_INT_243X_MCBSP2_IRQ 16 412 # define OMAP_INT_243X_MCBSP3_IRQ 17 413 # define OMAP_INT_243X_MCBSP4_IRQ 18 414 # define OMAP_INT_243X_MCBSP5_IRQ 19 415 # define OMAP_INT_24XX_GPMC_IRQ 20 416 # define OMAP_INT_24XX_GUFFAW_IRQ 21 417 # define OMAP_INT_24XX_IVA_IRQ 22 418 # define OMAP_INT_24XX_EAC_IRQ 23 419 # define OMAP_INT_24XX_CAM_IRQ 24 420 # define OMAP_INT_24XX_DSS_IRQ 25 421 # define OMAP_INT_24XX_MAIL_U0_MPU 26 422 # define OMAP_INT_24XX_DSP_UMA 27 423 # define OMAP_INT_24XX_DSP_MMU 28 424 # define OMAP_INT_24XX_GPIO_BANK1 29 425 # define OMAP_INT_24XX_GPIO_BANK2 30 426 # define OMAP_INT_24XX_GPIO_BANK3 31 427 # define OMAP_INT_24XX_GPIO_BANK4 32 428 # define OMAP_INT_243X_GPIO_BANK5 33 429 # define OMAP_INT_24XX_MAIL_U3_MPU 34 430 # define OMAP_INT_24XX_WDT3 35 431 # define OMAP_INT_24XX_WDT4 36 432 # define OMAP_INT_24XX_GPTIMER1 37 433 # define OMAP_INT_24XX_GPTIMER2 38 434 # define OMAP_INT_24XX_GPTIMER3 39 435 # define OMAP_INT_24XX_GPTIMER4 40 436 # define OMAP_INT_24XX_GPTIMER5 41 437 # define OMAP_INT_24XX_GPTIMER6 42 438 # define OMAP_INT_24XX_GPTIMER7 43 439 # define OMAP_INT_24XX_GPTIMER8 44 440 # define OMAP_INT_24XX_GPTIMER9 45 441 # define OMAP_INT_24XX_GPTIMER10 46 442 # define OMAP_INT_24XX_GPTIMER11 47 443 # define OMAP_INT_24XX_GPTIMER12 48 444 # define OMAP_INT_24XX_PKA_IRQ 50 445 # define OMAP_INT_24XX_SHA1MD5_IRQ 51 446 # define OMAP_INT_24XX_RNG_IRQ 52 447 # define OMAP_INT_24XX_MG_IRQ 53 448 # define OMAP_INT_24XX_I2C1_IRQ 56 449 # define OMAP_INT_24XX_I2C2_IRQ 57 450 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 451 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 452 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 453 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 454 # define OMAP_INT_243X_MCBSP1_IRQ 64 455 # define OMAP_INT_24XX_MCSPI1_IRQ 65 456 # define OMAP_INT_24XX_MCSPI2_IRQ 66 457 # define OMAP_INT_24XX_SSI1_IRQ0 67 458 # define OMAP_INT_24XX_SSI1_IRQ1 68 459 # define OMAP_INT_24XX_SSI2_IRQ0 69 460 # define OMAP_INT_24XX_SSI2_IRQ1 70 461 # define OMAP_INT_24XX_SSI_GDD_IRQ 71 462 # define OMAP_INT_24XX_UART1_IRQ 72 463 # define OMAP_INT_24XX_UART2_IRQ 73 464 # define OMAP_INT_24XX_UART3_IRQ 74 465 # define OMAP_INT_24XX_USB_IRQ_GEN 75 466 # define OMAP_INT_24XX_USB_IRQ_NISO 76 467 # define OMAP_INT_24XX_USB_IRQ_ISO 77 468 # define OMAP_INT_24XX_USB_IRQ_HGEN 78 469 # define OMAP_INT_24XX_USB_IRQ_HSOF 79 470 # define OMAP_INT_24XX_USB_IRQ_OTG 80 471 # define OMAP_INT_24XX_VLYNQ_IRQ 81 472 # define OMAP_INT_24XX_MMC_IRQ 83 473 # define OMAP_INT_24XX_MS_IRQ 84 474 # define OMAP_INT_24XX_FAC_IRQ 85 475 # define OMAP_INT_24XX_MCSPI3_IRQ 91 476 # define OMAP_INT_243X_HS_USB_MC 92 477 # define OMAP_INT_243X_HS_USB_DMA 93 478 # define OMAP_INT_243X_CARKIT 94 479 # define OMAP_INT_34XX_GPTIMER12 95 480 481 /* omap_dma.c */ 482 enum omap_dma_model { 483 omap_dma_3_0, 484 omap_dma_3_1, 485 omap_dma_3_2, 486 omap_dma_4, 487 }; 488 489 struct soc_dma_s; 490 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 491 MemoryRegion *sysmem, 492 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 493 enum omap_dma_model model); 494 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 495 MemoryRegion *sysmem, 496 struct omap_mpu_state_s *mpu, int fifo, 497 int chans, omap_clk iclk, omap_clk fclk); 498 void omap_dma_reset(struct soc_dma_s *s); 499 500 struct dma_irq_map { 501 int ih; 502 int intr; 503 }; 504 505 /* Only used in OMAP DMA 3.x gigacells */ 506 enum omap_dma_port { 507 emiff = 0, 508 emifs, 509 imif, /* omap16xx: ocp_t1 */ 510 tipb, 511 local, /* omap16xx: ocp_t2 */ 512 tipb_mpui, 513 __omap_dma_port_last, 514 }; 515 516 typedef enum { 517 constant = 0, 518 post_incremented, 519 single_index, 520 double_index, 521 } omap_dma_addressing_t; 522 523 /* Only used in OMAP DMA 3.x gigacells */ 524 struct omap_dma_lcd_channel_s { 525 enum omap_dma_port src; 526 hwaddr src_f1_top; 527 hwaddr src_f1_bottom; 528 hwaddr src_f2_top; 529 hwaddr src_f2_bottom; 530 531 /* Used in OMAP DMA 3.2 gigacell */ 532 unsigned char brust_f1; 533 unsigned char pack_f1; 534 unsigned char data_type_f1; 535 unsigned char brust_f2; 536 unsigned char pack_f2; 537 unsigned char data_type_f2; 538 unsigned char end_prog; 539 unsigned char repeat; 540 unsigned char auto_init; 541 unsigned char priority; 542 unsigned char fs; 543 unsigned char running; 544 unsigned char bs; 545 unsigned char omap_3_1_compatible_disable; 546 unsigned char dst; 547 unsigned char lch_type; 548 int16_t element_index_f1; 549 int16_t element_index_f2; 550 int32_t frame_index_f1; 551 int32_t frame_index_f2; 552 uint16_t elements_f1; 553 uint16_t frames_f1; 554 uint16_t elements_f2; 555 uint16_t frames_f2; 556 omap_dma_addressing_t mode_f1; 557 omap_dma_addressing_t mode_f2; 558 559 /* Destination port is fixed. */ 560 int interrupts; 561 int condition; 562 int dual; 563 564 int current_frame; 565 hwaddr phys_framebuffer[2]; 566 qemu_irq irq; 567 struct omap_mpu_state_s *mpu; 568 } *omap_dma_get_lcdch(struct soc_dma_s *s); 569 570 /* 571 * DMA request numbers for OMAP1 572 * See /usr/include/asm-arm/arch-omap/dma.h in Linux. 573 */ 574 # define OMAP_DMA_NO_DEVICE 0 575 # define OMAP_DMA_MCSI1_TX 1 576 # define OMAP_DMA_MCSI1_RX 2 577 # define OMAP_DMA_I2C_RX 3 578 # define OMAP_DMA_I2C_TX 4 579 # define OMAP_DMA_EXT_NDMA_REQ0 5 580 # define OMAP_DMA_EXT_NDMA_REQ1 6 581 # define OMAP_DMA_UWIRE_TX 7 582 # define OMAP_DMA_MCBSP1_TX 8 583 # define OMAP_DMA_MCBSP1_RX 9 584 # define OMAP_DMA_MCBSP3_TX 10 585 # define OMAP_DMA_MCBSP3_RX 11 586 # define OMAP_DMA_UART1_TX 12 587 # define OMAP_DMA_UART1_RX 13 588 # define OMAP_DMA_UART2_TX 14 589 # define OMAP_DMA_UART2_RX 15 590 # define OMAP_DMA_MCBSP2_TX 16 591 # define OMAP_DMA_MCBSP2_RX 17 592 # define OMAP_DMA_UART3_TX 18 593 # define OMAP_DMA_UART3_RX 19 594 # define OMAP_DMA_CAMERA_IF_RX 20 595 # define OMAP_DMA_MMC_TX 21 596 # define OMAP_DMA_MMC_RX 22 597 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ 598 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ 599 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ 600 # define OMAP_DMA_USB_W2FC_RX0 26 601 # define OMAP_DMA_USB_W2FC_RX1 27 602 # define OMAP_DMA_USB_W2FC_RX2 28 603 # define OMAP_DMA_USB_W2FC_TX0 29 604 # define OMAP_DMA_USB_W2FC_TX1 30 605 # define OMAP_DMA_USB_W2FC_TX2 31 606 607 /* These are only for 1610 */ 608 # define OMAP_DMA_CRYPTO_DES_IN 32 609 # define OMAP_DMA_SPI_TX 33 610 # define OMAP_DMA_SPI_RX 34 611 # define OMAP_DMA_CRYPTO_HASH 35 612 # define OMAP_DMA_CCP_ATTN 36 613 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 614 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 615 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 616 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 617 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 618 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 619 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 620 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 621 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 622 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 623 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 624 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 625 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 626 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 627 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 628 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 629 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 630 # define OMAP_DMA_MMC2_TX 54 631 # define OMAP_DMA_MMC2_RX 55 632 # define OMAP_DMA_CRYPTO_DES_OUT 56 633 634 /* 635 * DMA request numbers for the OMAP2 636 */ 637 # define OMAP24XX_DMA_NO_DEVICE 0 638 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ 639 # define OMAP24XX_DMA_EXT_DMAREQ0 2 640 # define OMAP24XX_DMA_EXT_DMAREQ1 3 641 # define OMAP24XX_DMA_GPMC 4 642 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ 643 # define OMAP24XX_DMA_DSS 6 644 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ 645 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ 646 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ 647 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ 648 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ 649 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ 650 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ 651 # define OMAP24XX_DMA_EXT_DMAREQ2 14 652 # define OMAP24XX_DMA_EXT_DMAREQ3 15 653 # define OMAP24XX_DMA_EXT_DMAREQ4 16 654 # define OMAP24XX_DMA_EAC_AC_RD 17 655 # define OMAP24XX_DMA_EAC_AC_WR 18 656 # define OMAP24XX_DMA_EAC_MD_UL_RD 19 657 # define OMAP24XX_DMA_EAC_MD_UL_WR 20 658 # define OMAP24XX_DMA_EAC_MD_DL_RD 21 659 # define OMAP24XX_DMA_EAC_MD_DL_WR 22 660 # define OMAP24XX_DMA_EAC_BT_UL_RD 23 661 # define OMAP24XX_DMA_EAC_BT_UL_WR 24 662 # define OMAP24XX_DMA_EAC_BT_DL_RD 25 663 # define OMAP24XX_DMA_EAC_BT_DL_WR 26 664 # define OMAP24XX_DMA_I2C1_TX 27 665 # define OMAP24XX_DMA_I2C1_RX 28 666 # define OMAP24XX_DMA_I2C2_TX 29 667 # define OMAP24XX_DMA_I2C2_RX 30 668 # define OMAP24XX_DMA_MCBSP1_TX 31 669 # define OMAP24XX_DMA_MCBSP1_RX 32 670 # define OMAP24XX_DMA_MCBSP2_TX 33 671 # define OMAP24XX_DMA_MCBSP2_RX 34 672 # define OMAP24XX_DMA_SPI1_TX0 35 673 # define OMAP24XX_DMA_SPI1_RX0 36 674 # define OMAP24XX_DMA_SPI1_TX1 37 675 # define OMAP24XX_DMA_SPI1_RX1 38 676 # define OMAP24XX_DMA_SPI1_TX2 39 677 # define OMAP24XX_DMA_SPI1_RX2 40 678 # define OMAP24XX_DMA_SPI1_TX3 41 679 # define OMAP24XX_DMA_SPI1_RX3 42 680 # define OMAP24XX_DMA_SPI2_TX0 43 681 # define OMAP24XX_DMA_SPI2_RX0 44 682 # define OMAP24XX_DMA_SPI2_TX1 45 683 # define OMAP24XX_DMA_SPI2_RX1 46 684 685 # define OMAP24XX_DMA_UART1_TX 49 686 # define OMAP24XX_DMA_UART1_RX 50 687 # define OMAP24XX_DMA_UART2_TX 51 688 # define OMAP24XX_DMA_UART2_RX 52 689 # define OMAP24XX_DMA_UART3_TX 53 690 # define OMAP24XX_DMA_UART3_RX 54 691 # define OMAP24XX_DMA_USB_W2FC_TX0 55 692 # define OMAP24XX_DMA_USB_W2FC_RX0 56 693 # define OMAP24XX_DMA_USB_W2FC_TX1 57 694 # define OMAP24XX_DMA_USB_W2FC_RX1 58 695 # define OMAP24XX_DMA_USB_W2FC_TX2 59 696 # define OMAP24XX_DMA_USB_W2FC_RX2 60 697 # define OMAP24XX_DMA_MMC1_TX 61 698 # define OMAP24XX_DMA_MMC1_RX 62 699 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ 700 # define OMAP24XX_DMA_EXT_DMAREQ5 64 701 702 /* omap[123].c */ 703 /* OMAP2 gp timer */ 704 struct omap_gp_timer_s; 705 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, 706 qemu_irq irq, omap_clk fclk, omap_clk iclk); 707 void omap_gp_timer_reset(struct omap_gp_timer_s *s); 708 709 /* OMAP2 sysctimer */ 710 struct omap_synctimer_s; 711 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, 712 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); 713 void omap_synctimer_reset(struct omap_synctimer_s *s); 714 715 struct omap_uart_s; 716 struct omap_uart_s *omap_uart_init(hwaddr base, 717 qemu_irq irq, omap_clk fclk, omap_clk iclk, 718 qemu_irq txdma, qemu_irq rxdma, 719 const char *label, Chardev *chr); 720 struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, 721 struct omap_target_agent_s *ta, 722 qemu_irq irq, omap_clk fclk, omap_clk iclk, 723 qemu_irq txdma, qemu_irq rxdma, 724 const char *label, Chardev *chr); 725 void omap_uart_reset(struct omap_uart_s *s); 726 727 struct omap_mpuio_s; 728 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); 729 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); 730 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); 731 732 typedef struct uWireSlave { 733 uint16_t (*receive)(void *opaque); 734 void (*send)(void *opaque, uint16_t data); 735 void *opaque; 736 } uWireSlave; 737 738 struct omap_uwire_s; 739 void omap_uwire_attach(struct omap_uwire_s *s, 740 uWireSlave *slave, int chipselect); 741 742 /* OMAP2 spi */ 743 struct omap_mcspi_s; 744 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, 745 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); 746 void omap_mcspi_attach(struct omap_mcspi_s *s, 747 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, 748 int chipselect); 749 void omap_mcspi_reset(struct omap_mcspi_s *s); 750 751 struct I2SCodec { 752 void *opaque; 753 754 /* The CPU can call this if it is generating the clock signal on the 755 * i2s port. The CODEC can ignore it if it is set up as a clock 756 * master and generates its own clock. */ 757 void (*set_rate)(void *opaque, int in, int out); 758 759 void (*tx_swallow)(void *opaque); 760 qemu_irq rx_swallow; 761 qemu_irq tx_start; 762 763 int tx_rate; 764 int cts; 765 int rx_rate; 766 int rts; 767 768 struct i2s_fifo_s { 769 uint8_t *fifo; 770 int len; 771 int start; 772 int size; 773 } in, out; 774 }; 775 struct omap_mcbsp_s; 776 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); 777 778 void omap_tap_init(struct omap_target_agent_s *ta, 779 struct omap_mpu_state_s *mpu); 780 781 /* omap_lcdc.c */ 782 struct omap_lcd_panel_s; 783 void omap_lcdc_reset(struct omap_lcd_panel_s *s); 784 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 785 hwaddr base, 786 qemu_irq irq, 787 struct omap_dma_lcd_channel_s *dma, 788 omap_clk clk); 789 790 /* omap_dss.c */ 791 struct rfbi_chip_s { 792 void *opaque; 793 void (*write)(void *opaque, int dc, uint16_t value); 794 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); 795 uint16_t (*read)(void *opaque, int dc); 796 }; 797 struct omap_dss_s; 798 void omap_dss_reset(struct omap_dss_s *s); 799 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, 800 MemoryRegion *sysmem, 801 hwaddr l3_base, 802 qemu_irq irq, qemu_irq drq, 803 omap_clk fck1, omap_clk fck2, omap_clk ck54m, 804 omap_clk ick1, omap_clk ick2); 805 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); 806 807 /* omap_mmc.c */ 808 struct omap_mmc_s; 809 struct omap_mmc_s *omap_mmc_init(hwaddr base, 810 MemoryRegion *sysmem, 811 BlockBackend *blk, 812 qemu_irq irq, qemu_irq dma[], omap_clk clk); 813 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 814 BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 815 omap_clk fclk, omap_clk iclk); 816 void omap_mmc_reset(struct omap_mmc_s *s); 817 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); 818 void omap_mmc_enable(struct omap_mmc_s *s, int enable); 819 820 /* omap_i2c.c */ 821 I2CBus *omap_i2c_bus(DeviceState *omap_i2c); 822 823 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) 824 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) 825 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) 826 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) 827 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) 828 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) 829 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) 830 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) 831 # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) 832 833 # define cpu_is_omap15xx(cpu) \ 834 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) 835 # define cpu_is_omap16xx(cpu) \ 836 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) 837 # define cpu_is_omap24xx(cpu) \ 838 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) 839 840 # define cpu_class_omap1(cpu) \ 841 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) 842 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) 843 # define cpu_class_omap3(cpu) \ 844 (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) 845 846 struct omap_mpu_state_s { 847 enum omap_mpu_model { 848 omap310, 849 omap1510, 850 omap1610, 851 omap1710, 852 omap2410, 853 omap2420, 854 omap2422, 855 omap2423, 856 omap2430, 857 omap3430, 858 omap3630, 859 } mpu_model; 860 861 ARMCPU *cpu; 862 863 qemu_irq *drq; 864 865 qemu_irq wakeup; 866 867 MemoryRegion ulpd_pm_iomem; 868 MemoryRegion pin_cfg_iomem; 869 MemoryRegion id_iomem; 870 MemoryRegion id_iomem_e18; 871 MemoryRegion id_iomem_ed4; 872 MemoryRegion id_iomem_e20; 873 MemoryRegion mpui_iomem; 874 MemoryRegion tcmi_iomem; 875 MemoryRegion clkm_iomem; 876 MemoryRegion clkdsp_iomem; 877 MemoryRegion mpui_io_iomem; 878 MemoryRegion tap_iomem; 879 MemoryRegion imif_ram; 880 MemoryRegion sram; 881 882 struct omap_dma_port_if_s { 883 uint32_t (*read[3])(struct omap_mpu_state_s *s, 884 hwaddr offset); 885 void (*write[3])(struct omap_mpu_state_s *s, 886 hwaddr offset, uint32_t value); 887 int (*addr_valid)(struct omap_mpu_state_s *s, 888 hwaddr addr); 889 } port[__omap_dma_port_last]; 890 891 uint64_t sdram_size; 892 unsigned long sram_size; 893 894 /* MPUI-TIPB peripherals */ 895 struct omap_uart_s *uart[3]; 896 897 DeviceState *gpio; 898 899 struct omap_mcbsp_s *mcbsp1; 900 struct omap_mcbsp_s *mcbsp3; 901 902 /* MPU public TIPB peripherals */ 903 struct omap_32khz_timer_s *os_timer; 904 905 struct omap_mmc_s *mmc; 906 907 struct omap_mpuio_s *mpuio; 908 909 struct omap_uwire_s *microwire; 910 911 struct omap_pwl_s *pwl; 912 struct omap_pwt_s *pwt; 913 DeviceState *i2c[2]; 914 915 struct omap_rtc_s *rtc; 916 917 struct omap_mcbsp_s *mcbsp2; 918 919 struct omap_lpg_s *led[2]; 920 921 /* MPU private TIPB peripherals */ 922 DeviceState *ih[2]; 923 924 struct soc_dma_s *dma; 925 926 struct omap_mpu_timer_s *timer[3]; 927 struct omap_watchdog_timer_s *wdt; 928 929 struct omap_lcd_panel_s *lcd; 930 931 uint32_t ulpd_pm_regs[21]; 932 int64_t ulpd_gauge_start; 933 934 uint32_t func_mux_ctrl[14]; 935 uint32_t comp_mode_ctrl[1]; 936 uint32_t pull_dwn_ctrl[4]; 937 uint32_t gate_inh_ctrl[1]; 938 uint32_t voltage_ctrl[1]; 939 uint32_t test_dbg_ctrl[1]; 940 uint32_t mod_conf_ctrl[1]; 941 int compat1509; 942 943 uint32_t mpui_ctrl; 944 945 struct omap_tipb_bridge_s *private_tipb; 946 struct omap_tipb_bridge_s *public_tipb; 947 948 uint32_t tcmi_regs[17]; 949 950 struct dpll_ctl_s *dpll[3]; 951 952 omap_clk clks; 953 struct { 954 int cold_start; 955 int clocking_scheme; 956 uint16_t arm_ckctl; 957 uint16_t arm_idlect1; 958 uint16_t arm_idlect2; 959 uint16_t arm_ewupct; 960 uint16_t arm_rstct1; 961 uint16_t arm_rstct2; 962 uint16_t arm_ckout1; 963 int dpll1_mode; 964 uint16_t dsp_idlect1; 965 uint16_t dsp_idlect2; 966 uint16_t dsp_rstct2; 967 } clkm; 968 969 /* OMAP2-only peripherals */ 970 struct omap_l4_s *l4; 971 972 struct omap_gp_timer_s *gptimer[12]; 973 struct omap_synctimer_s *synctimer; 974 975 struct omap_prcm_s *prcm; 976 struct omap_sdrc_s *sdrc; 977 struct omap_gpmc_s *gpmc; 978 struct omap_sysctl_s *sysc; 979 980 struct omap_mcspi_s *mcspi[2]; 981 982 struct omap_dss_s *dss; 983 984 struct omap_eac_s *eac; 985 }; 986 987 /* omap1.c */ 988 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, 989 const char *core); 990 991 /* omap2.c */ 992 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, 993 const char *core); 994 995 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); 996 void omap_badwidth_write8(void *opaque, hwaddr addr, 997 uint32_t value); 998 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); 999 void omap_badwidth_write16(void *opaque, hwaddr addr, 1000 uint32_t value); 1001 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); 1002 void omap_badwidth_write32(void *opaque, hwaddr addr, 1003 uint32_t value); 1004 1005 void omap_mpu_wakeup(void *opaque, int irq, int req); 1006 1007 # define OMAP_BAD_REG(paddr) \ 1008 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ 1009 __func__, paddr) 1010 # define OMAP_RO_REG(paddr) \ 1011 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ 1012 HWADDR_PRIx "\n", \ 1013 __func__, paddr) 1014 1015 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area 1016 * (Board-specific tags are not here) 1017 */ 1018 #define OMAP_TAG_CLOCK 0x4f01 1019 #define OMAP_TAG_MMC 0x4f02 1020 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 1021 #define OMAP_TAG_USB 0x4f04 1022 #define OMAP_TAG_LCD 0x4f05 1023 #define OMAP_TAG_GPIO_SWITCH 0x4f06 1024 #define OMAP_TAG_UART 0x4f07 1025 #define OMAP_TAG_FBMEM 0x4f08 1026 #define OMAP_TAG_STI_CONSOLE 0x4f09 1027 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a 1028 #define OMAP_TAG_PARTITION 0x4f0b 1029 #define OMAP_TAG_TEA5761 0x4f10 1030 #define OMAP_TAG_TMP105 0x4f11 1031 #define OMAP_TAG_BOOT_REASON 0x4f80 1032 #define OMAP_TAG_FLASH_PART_STR 0x4f81 1033 #define OMAP_TAG_VERSION_STR 0x4f82 1034 1035 enum { 1036 OMAP_GPIOSW_TYPE_COVER = 0 << 4, 1037 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, 1038 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, 1039 }; 1040 1041 #define OMAP_GPIOSW_INVERTED 0x0001 1042 #define OMAP_GPIOSW_OUTPUT 0x0002 1043 1044 # define OMAP_MPUI_REG_MASK 0x000007ff 1045 1046 #endif 1047