1 /* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 #ifndef NPCM7XX_H 17 #define NPCM7XX_H 18 19 #include "hw/boards.h" 20 #include "hw/cpu/a9mpcore.h" 21 #include "hw/misc/npcm7xx_clk.h" 22 #include "hw/misc/npcm7xx_gcr.h" 23 #include "hw/timer/npcm7xx_timer.h" 24 #include "target/arm/cpu.h" 25 26 #define NPCM7XX_MAX_NUM_CPUS (2) 27 28 /* The first half of the address space is reserved for DDR4 DRAM. */ 29 #define NPCM7XX_DRAM_BA (0x00000000) 30 #define NPCM7XX_DRAM_SZ (2 * GiB) 31 32 /* Magic addresses for setting up direct kernel booting and SMP boot stubs. */ 33 #define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */ 34 #define NPCM7XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */ 35 #define NPCM7XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */ 36 #define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */ 37 38 typedef struct NPCM7xxMachine { 39 MachineState parent; 40 } NPCM7xxMachine; 41 42 #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") 43 #define NPCM7XX_MACHINE(obj) \ 44 OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE) 45 46 typedef struct NPCM7xxMachineClass { 47 MachineClass parent; 48 49 const char *soc_type; 50 } NPCM7xxMachineClass; 51 52 #define NPCM7XX_MACHINE_CLASS(klass) \ 53 OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE) 54 #define NPCM7XX_MACHINE_GET_CLASS(obj) \ 55 OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE) 56 57 typedef struct NPCM7xxState { 58 DeviceState parent; 59 60 ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS]; 61 A9MPPrivState a9mpcore; 62 63 MemoryRegion sram; 64 MemoryRegion irom; 65 MemoryRegion ram3; 66 MemoryRegion *dram; 67 68 NPCM7xxGCRState gcr; 69 NPCM7xxCLKState clk; 70 NPCM7xxTimerCtrlState tim[3]; 71 } NPCM7xxState; 72 73 #define TYPE_NPCM7XX "npcm7xx" 74 #define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) 75 76 #define TYPE_NPCM730 "npcm730" 77 #define TYPE_NPCM750 "npcm750" 78 79 typedef struct NPCM7xxClass { 80 DeviceClass parent; 81 82 /* Bitmask of modules that are permanently disabled on this chip. */ 83 uint32_t disabled_modules; 84 /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */ 85 uint32_t num_cpus; 86 } NPCM7xxClass; 87 88 #define NPCM7XX_CLASS(klass) \ 89 OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX) 90 #define NPCM7XX_GET_CLASS(obj) \ 91 OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX) 92 93 /** 94 * npcm7xx_load_kernel - Loads memory with everything needed to boot 95 * @machine - The machine containing the SoC to be booted. 96 * @soc - The SoC containing the CPU to be booted. 97 * 98 * This will set up the ARM boot info structure for the specific NPCM7xx 99 * derivative and call arm_load_kernel() to set up loading of the kernel, etc. 100 * into memory, if requested by the user. 101 */ 102 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc); 103 104 #endif /* NPCM7XX_H */ 105