1 /* 2 * i.MX 8M Plus SoC Definitions 3 * 4 * Copyright (c) 2024, Bernhard Beschow <shentey@gmail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #ifndef FSL_IMX8MP_H 10 #define FSL_IMX8MP_H 11 12 #include "cpu.h" 13 #include "hw/char/imx_serial.h" 14 #include "hw/gpio/imx_gpio.h" 15 #include "hw/intc/arm_gicv3_common.h" 16 #include "hw/misc/imx7_snvs.h" 17 #include "hw/misc/imx8mp_analog.h" 18 #include "hw/misc/imx8mp_ccm.h" 19 #include "hw/pci-host/designware.h" 20 #include "hw/pci-host/fsl_imx8m_phy.h" 21 #include "hw/sd/sdhci.h" 22 #include "qom/object.h" 23 #include "qemu/units.h" 24 25 #define TYPE_FSL_IMX8MP "fsl-imx8mp" 26 OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP) 27 28 #define FSL_IMX8MP_RAM_START 0x40000000 29 #define FSL_IMX8MP_RAM_SIZE_MAX (8 * GiB) 30 31 enum FslImx8mpConfiguration { 32 FSL_IMX8MP_NUM_CPUS = 4, 33 FSL_IMX8MP_NUM_GPIOS = 5, 34 FSL_IMX8MP_NUM_IRQS = 160, 35 FSL_IMX8MP_NUM_UARTS = 4, 36 FSL_IMX8MP_NUM_USDHCS = 3, 37 }; 38 39 struct FslImx8mpState { 40 DeviceState parent_obj; 41 42 ARMCPU cpu[FSL_IMX8MP_NUM_CPUS]; 43 GICv3State gic; 44 IMXGPIOState gpio[FSL_IMX8MP_NUM_GPIOS]; 45 IMX8MPCCMState ccm; 46 IMX8MPAnalogState analog; 47 IMX7SNVSState snvs; 48 IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; 49 SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS]; 50 DesignwarePCIEHost pcie; 51 FslImx8mPciePhyState pcie_phy; 52 }; 53 54 enum FslImx8mpMemoryRegions { 55 FSL_IMX8MP_A53_DAP, 56 FSL_IMX8MP_AIPS1_CONFIGURATION, 57 FSL_IMX8MP_AIPS2_CONFIGURATION, 58 FSL_IMX8MP_AIPS3_CONFIGURATION, 59 FSL_IMX8MP_AIPS4_CONFIGURATION, 60 FSL_IMX8MP_AIPS5_CONFIGURATION, 61 FSL_IMX8MP_ANA_OSC, 62 FSL_IMX8MP_ANA_PLL, 63 FSL_IMX8MP_ANA_TSENSOR, 64 FSL_IMX8MP_APBH_DMA, 65 FSL_IMX8MP_ASRC, 66 FSL_IMX8MP_AUDIO_BLK_CTRL, 67 FSL_IMX8MP_AUDIO_DSP, 68 FSL_IMX8MP_AUDIO_XCVR_RX, 69 FSL_IMX8MP_AUD_IRQ_STEER, 70 FSL_IMX8MP_BOOT_ROM, 71 FSL_IMX8MP_BOOT_ROM_PROTECTED, 72 FSL_IMX8MP_CAAM, 73 FSL_IMX8MP_CAAM_MEM, 74 FSL_IMX8MP_CCM, 75 FSL_IMX8MP_CSU, 76 FSL_IMX8MP_DDR_BLK_CTRL, 77 FSL_IMX8MP_DDR_CTL, 78 FSL_IMX8MP_DDR_PERF_MON, 79 FSL_IMX8MP_DDR_PHY, 80 FSL_IMX8MP_DDR_PHY_BROADCAST, 81 FSL_IMX8MP_ECSPI1, 82 FSL_IMX8MP_ECSPI2, 83 FSL_IMX8MP_ECSPI3, 84 FSL_IMX8MP_EDMA_CHANNELS, 85 FSL_IMX8MP_EDMA_MANAGEMENT_PAGE, 86 FSL_IMX8MP_ENET1, 87 FSL_IMX8MP_ENET2_TSN, 88 FSL_IMX8MP_FLEXCAN1, 89 FSL_IMX8MP_FLEXCAN2, 90 FSL_IMX8MP_GIC_DIST, 91 FSL_IMX8MP_GIC_REDIST, 92 FSL_IMX8MP_GPC, 93 FSL_IMX8MP_GPIO1, 94 FSL_IMX8MP_GPIO2, 95 FSL_IMX8MP_GPIO3, 96 FSL_IMX8MP_GPIO4, 97 FSL_IMX8MP_GPIO5, 98 FSL_IMX8MP_GPT1, 99 FSL_IMX8MP_GPT2, 100 FSL_IMX8MP_GPT3, 101 FSL_IMX8MP_GPT4, 102 FSL_IMX8MP_GPT5, 103 FSL_IMX8MP_GPT6, 104 FSL_IMX8MP_GPU2D, 105 FSL_IMX8MP_GPU3D, 106 FSL_IMX8MP_HDMI_TX, 107 FSL_IMX8MP_HDMI_TX_AUDLNK_MSTR, 108 FSL_IMX8MP_HSIO_BLK_CTL, 109 FSL_IMX8MP_I2C1, 110 FSL_IMX8MP_I2C2, 111 FSL_IMX8MP_I2C3, 112 FSL_IMX8MP_I2C4, 113 FSL_IMX8MP_I2C5, 114 FSL_IMX8MP_I2C6, 115 FSL_IMX8MP_INTERCONNECT, 116 FSL_IMX8MP_IOMUXC, 117 FSL_IMX8MP_IOMUXC_GPR, 118 FSL_IMX8MP_IPS_DEWARP, 119 FSL_IMX8MP_ISI, 120 FSL_IMX8MP_ISP1, 121 FSL_IMX8MP_ISP2, 122 FSL_IMX8MP_LCDIF1, 123 FSL_IMX8MP_LCDIF2, 124 FSL_IMX8MP_MEDIA_BLK_CTL, 125 FSL_IMX8MP_MIPI_CSI1, 126 FSL_IMX8MP_MIPI_CSI2, 127 FSL_IMX8MP_MIPI_DSI1, 128 FSL_IMX8MP_MU_1_A, 129 FSL_IMX8MP_MU_1_B, 130 FSL_IMX8MP_MU_2_A, 131 FSL_IMX8MP_MU_2_B, 132 FSL_IMX8MP_MU_3_A, 133 FSL_IMX8MP_MU_3_B, 134 FSL_IMX8MP_NPU, 135 FSL_IMX8MP_OCOTP_CTRL, 136 FSL_IMX8MP_OCRAM, 137 FSL_IMX8MP_OCRAM_S, 138 FSL_IMX8MP_PCIE1, 139 FSL_IMX8MP_PCIE1_MEM, 140 FSL_IMX8MP_PCIE_PHY1, 141 FSL_IMX8MP_PDM, 142 FSL_IMX8MP_PERFMON1, 143 FSL_IMX8MP_PERFMON2, 144 FSL_IMX8MP_PWM1, 145 FSL_IMX8MP_PWM2, 146 FSL_IMX8MP_PWM3, 147 FSL_IMX8MP_PWM4, 148 FSL_IMX8MP_QOSC, 149 FSL_IMX8MP_QSPI, 150 FSL_IMX8MP_QSPI1_RX_BUFFER, 151 FSL_IMX8MP_QSPI1_TX_BUFFER, 152 FSL_IMX8MP_QSPI_MEM, 153 FSL_IMX8MP_RAM, 154 FSL_IMX8MP_RDC, 155 FSL_IMX8MP_SAI1, 156 FSL_IMX8MP_SAI2, 157 FSL_IMX8MP_SAI3, 158 FSL_IMX8MP_SAI5, 159 FSL_IMX8MP_SAI6, 160 FSL_IMX8MP_SAI7, 161 FSL_IMX8MP_SDMA1, 162 FSL_IMX8MP_SDMA2, 163 FSL_IMX8MP_SDMA3, 164 FSL_IMX8MP_SEMAPHORE1, 165 FSL_IMX8MP_SEMAPHORE2, 166 FSL_IMX8MP_SEMAPHORE_HS, 167 FSL_IMX8MP_SNVS_HP, 168 FSL_IMX8MP_SPBA1, 169 FSL_IMX8MP_SPBA2, 170 FSL_IMX8MP_SRC, 171 FSL_IMX8MP_SYSCNT_CMP, 172 FSL_IMX8MP_SYSCNT_CTRL, 173 FSL_IMX8MP_SYSCNT_RD, 174 FSL_IMX8MP_TCM_DTCM, 175 FSL_IMX8MP_TCM_ITCM, 176 FSL_IMX8MP_TZASC, 177 FSL_IMX8MP_UART1, 178 FSL_IMX8MP_UART2, 179 FSL_IMX8MP_UART3, 180 FSL_IMX8MP_UART4, 181 FSL_IMX8MP_USB1, 182 FSL_IMX8MP_USB2, 183 FSL_IMX8MP_USDHC1, 184 FSL_IMX8MP_USDHC2, 185 FSL_IMX8MP_USDHC3, 186 FSL_IMX8MP_VPU, 187 FSL_IMX8MP_VPU_BLK_CTRL, 188 FSL_IMX8MP_VPU_G1_DECODER, 189 FSL_IMX8MP_VPU_G2_DECODER, 190 FSL_IMX8MP_VPU_VC8000E_ENCODER, 191 FSL_IMX8MP_WDOG1, 192 FSL_IMX8MP_WDOG2, 193 FSL_IMX8MP_WDOG3, 194 }; 195 196 enum FslImx8mpIrqs { 197 FSL_IMX8MP_USDHC1_IRQ = 22, 198 FSL_IMX8MP_USDHC2_IRQ = 23, 199 FSL_IMX8MP_USDHC3_IRQ = 24, 200 201 FSL_IMX8MP_UART1_IRQ = 26, 202 FSL_IMX8MP_UART2_IRQ = 27, 203 FSL_IMX8MP_UART3_IRQ = 28, 204 FSL_IMX8MP_UART4_IRQ = 29, 205 FSL_IMX8MP_UART5_IRQ = 30, 206 FSL_IMX8MP_UART6_IRQ = 16, 207 208 FSL_IMX8MP_GPIO1_LOW_IRQ = 64, 209 FSL_IMX8MP_GPIO1_HIGH_IRQ = 65, 210 FSL_IMX8MP_GPIO2_LOW_IRQ = 66, 211 FSL_IMX8MP_GPIO2_HIGH_IRQ = 67, 212 FSL_IMX8MP_GPIO3_LOW_IRQ = 68, 213 FSL_IMX8MP_GPIO3_HIGH_IRQ = 69, 214 FSL_IMX8MP_GPIO4_LOW_IRQ = 70, 215 FSL_IMX8MP_GPIO4_HIGH_IRQ = 71, 216 FSL_IMX8MP_GPIO5_LOW_IRQ = 72, 217 FSL_IMX8MP_GPIO5_HIGH_IRQ = 73, 218 219 FSL_IMX8MP_PCI_INTA_IRQ = 126, 220 FSL_IMX8MP_PCI_INTB_IRQ = 125, 221 FSL_IMX8MP_PCI_INTC_IRQ = 124, 222 FSL_IMX8MP_PCI_INTD_IRQ = 123, 223 FSL_IMX8MP_PCI_MSI_IRQ = 140, 224 }; 225 226 #endif /* FSL_IMX8MP_H */ 227