1 /* 2 * Copyright (c) 2018, Impinj, Inc. 3 * 4 * i.MX7 SoC definitions 5 * 6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef FSL_IMX7_H 20 #define FSL_IMX7_H 21 22 #include "hw/cpu/a15mpcore.h" 23 #include "hw/intc/imx_gpcv2.h" 24 #include "hw/misc/imx7_ccm.h" 25 #include "hw/misc/imx7_snvs.h" 26 #include "hw/misc/imx7_gpr.h" 27 #include "hw/misc/imx7_src.h" 28 #include "hw/watchdog/wdt_imx2.h" 29 #include "hw/gpio/imx_gpio.h" 30 #include "hw/char/imx_serial.h" 31 #include "hw/timer/imx_gpt.h" 32 #include "hw/timer/imx_epit.h" 33 #include "hw/i2c/imx_i2c.h" 34 #include "hw/sd/sdhci.h" 35 #include "hw/ssi/imx_spi.h" 36 #include "hw/net/imx_fec.h" 37 #include "hw/pci-host/designware.h" 38 #include "hw/usb/chipidea.h" 39 #include "hw/or-irq.h" 40 #include "cpu.h" 41 #include "qom/object.h" 42 #include "qemu/units.h" 43 44 #define TYPE_FSL_IMX7 "fsl-imx7" 45 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7) 46 47 enum FslIMX7Configuration { 48 FSL_IMX7_NUM_CPUS = 2, 49 FSL_IMX7_NUM_UARTS = 7, 50 FSL_IMX7_NUM_ETHS = 2, 51 FSL_IMX7_ETH_NUM_TX_RINGS = 3, 52 FSL_IMX7_NUM_USDHCS = 3, 53 FSL_IMX7_NUM_WDTS = 4, 54 FSL_IMX7_NUM_GPTS = 4, 55 FSL_IMX7_NUM_IOMUXCS = 2, 56 FSL_IMX7_NUM_GPIOS = 7, 57 FSL_IMX7_NUM_I2CS = 4, 58 FSL_IMX7_NUM_ECSPIS = 4, 59 FSL_IMX7_NUM_USBS = 3, 60 FSL_IMX7_NUM_ADCS = 2, 61 FSL_IMX7_NUM_SAIS = 3, 62 FSL_IMX7_NUM_CANS = 2, 63 FSL_IMX7_NUM_PWMS = 4, 64 }; 65 66 struct FslIMX7State { 67 /*< private >*/ 68 DeviceState parent_obj; 69 70 /*< public >*/ 71 ARMCPU cpu[FSL_IMX7_NUM_CPUS]; 72 A15MPPrivState a7mpcore; 73 IMXGPTState gpt[FSL_IMX7_NUM_GPTS]; 74 IMXGPIOState gpio[FSL_IMX7_NUM_GPIOS]; 75 IMX7CCMState ccm; 76 IMX7AnalogState analog; 77 IMX7SNVSState snvs; 78 IMX7SRCState src; 79 IMXGPCv2State gpcv2; 80 IMXSPIState spi[FSL_IMX7_NUM_ECSPIS]; 81 IMXI2CState i2c[FSL_IMX7_NUM_I2CS]; 82 IMXSerialState uart[FSL_IMX7_NUM_UARTS]; 83 IMXFECState eth[FSL_IMX7_NUM_ETHS]; 84 SDHCIState usdhc[FSL_IMX7_NUM_USDHCS]; 85 IMX2WdtState wdt[FSL_IMX7_NUM_WDTS]; 86 IMX7GPRState gpr; 87 ChipideaState usb[FSL_IMX7_NUM_USBS]; 88 DesignwarePCIEHost pcie; 89 OrIRQState pcie4_msi_irq; 90 MemoryRegion rom; 91 MemoryRegion caam; 92 MemoryRegion ocram; 93 MemoryRegion ocram_epdc; 94 MemoryRegion ocram_pxp; 95 MemoryRegion ocram_s; 96 97 uint32_t phy_num[FSL_IMX7_NUM_ETHS]; 98 bool phy_connected[FSL_IMX7_NUM_ETHS]; 99 }; 100 101 enum FslIMX7MemoryMap { 102 FSL_IMX7_MMDC_ADDR = 0x80000000, 103 FSL_IMX7_MMDC_SIZE = (2 * GiB), 104 105 FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000, 106 FSL_IMX7_QSPI1_MEM_SIZE = (256 * MiB), 107 108 FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000, 109 FSL_IMX7_PCIE1_MEM_SIZE = (256 * MiB), 110 111 FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000, 112 FSL_IMX7_QSPI1_RX_BUF_SIZE = (32 * MiB), 113 114 /* PCIe Peripherals */ 115 FSL_IMX7_PCIE_REG_ADDR = 0x33800000, 116 117 /* MMAP Peripherals */ 118 FSL_IMX7_DMA_APBH_ADDR = 0x33000000, 119 FSL_IMX7_DMA_APBH_SIZE = 0x8000, 120 121 /* GPV configuration */ 122 FSL_IMX7_GPV6_ADDR = 0x32600000, 123 FSL_IMX7_GPV5_ADDR = 0x32500000, 124 FSL_IMX7_GPV4_ADDR = 0x32400000, 125 FSL_IMX7_GPV3_ADDR = 0x32300000, 126 FSL_IMX7_GPV2_ADDR = 0x32200000, 127 FSL_IMX7_GPV1_ADDR = 0x32100000, 128 FSL_IMX7_GPV0_ADDR = 0x32000000, 129 FSL_IMX7_GPVn_SIZE = (1 * MiB), 130 131 /* Arm Peripherals */ 132 FSL_IMX7_A7MPCORE_ADDR = 0x31000000, 133 134 /* AIPS-3 Begin */ 135 136 FSL_IMX7_ENET2_ADDR = 0x30BF0000, 137 FSL_IMX7_ENET1_ADDR = 0x30BE0000, 138 139 FSL_IMX7_SDMA_ADDR = 0x30BD0000, 140 FSL_IMX7_SDMA_SIZE = (4 * KiB), 141 142 FSL_IMX7_EIM_ADDR = 0x30BC0000, 143 FSL_IMX7_EIM_SIZE = (4 * KiB), 144 145 FSL_IMX7_QSPI_ADDR = 0x30BB0000, 146 FSL_IMX7_QSPI_SIZE = 0x8000, 147 148 FSL_IMX7_SIM2_ADDR = 0x30BA0000, 149 FSL_IMX7_SIM1_ADDR = 0x30B90000, 150 FSL_IMX7_SIMn_SIZE = (4 * KiB), 151 152 FSL_IMX7_USDHC3_ADDR = 0x30B60000, 153 FSL_IMX7_USDHC2_ADDR = 0x30B50000, 154 FSL_IMX7_USDHC1_ADDR = 0x30B40000, 155 156 FSL_IMX7_USB3_ADDR = 0x30B30000, 157 FSL_IMX7_USBMISC3_ADDR = 0x30B30200, 158 FSL_IMX7_USB2_ADDR = 0x30B20000, 159 FSL_IMX7_USBMISC2_ADDR = 0x30B20200, 160 FSL_IMX7_USB1_ADDR = 0x30B10000, 161 FSL_IMX7_USBMISC1_ADDR = 0x30B10200, 162 FSL_IMX7_USBMISCn_SIZE = 0x200, 163 164 FSL_IMX7_USB_PL301_ADDR = 0x30AD0000, 165 FSL_IMX7_USB_PL301_SIZE = (64 * KiB), 166 167 FSL_IMX7_SEMAPHORE_HS_ADDR = 0x30AC0000, 168 FSL_IMX7_SEMAPHORE_HS_SIZE = (64 * KiB), 169 170 FSL_IMX7_MUB_ADDR = 0x30AB0000, 171 FSL_IMX7_MUA_ADDR = 0x30AA0000, 172 FSL_IMX7_MUn_SIZE = (KiB), 173 174 FSL_IMX7_UART7_ADDR = 0x30A90000, 175 FSL_IMX7_UART6_ADDR = 0x30A80000, 176 FSL_IMX7_UART5_ADDR = 0x30A70000, 177 FSL_IMX7_UART4_ADDR = 0x30A60000, 178 179 FSL_IMX7_I2C4_ADDR = 0x30A50000, 180 FSL_IMX7_I2C3_ADDR = 0x30A40000, 181 FSL_IMX7_I2C2_ADDR = 0x30A30000, 182 FSL_IMX7_I2C1_ADDR = 0x30A20000, 183 184 FSL_IMX7_CAN2_ADDR = 0x30A10000, 185 FSL_IMX7_CAN1_ADDR = 0x30A00000, 186 FSL_IMX7_CANn_SIZE = (4 * KiB), 187 188 FSL_IMX7_AIPS3_CONF_ADDR = 0x309F0000, 189 FSL_IMX7_AIPS3_CONF_SIZE = (64 * KiB), 190 191 FSL_IMX7_CAAM_ADDR = 0x30900000, 192 FSL_IMX7_CAAM_SIZE = (256 * KiB), 193 194 FSL_IMX7_SPBA_ADDR = 0x308F0000, 195 FSL_IMX7_SPBA_SIZE = (4 * KiB), 196 197 FSL_IMX7_SAI3_ADDR = 0x308C0000, 198 FSL_IMX7_SAI2_ADDR = 0x308B0000, 199 FSL_IMX7_SAI1_ADDR = 0x308A0000, 200 FSL_IMX7_SAIn_SIZE = (4 * KiB), 201 202 FSL_IMX7_UART3_ADDR = 0x30880000, 203 /* 204 * Some versions of the reference manual claim that UART2 is @ 205 * 0x30870000, but experiments with HW + DT files in upstream 206 * Linux kernel show that not to be true and that block is 207 * actually located @ 0x30890000 208 */ 209 FSL_IMX7_UART2_ADDR = 0x30890000, 210 FSL_IMX7_UART1_ADDR = 0x30860000, 211 212 FSL_IMX7_ECSPI3_ADDR = 0x30840000, 213 FSL_IMX7_ECSPI2_ADDR = 0x30830000, 214 FSL_IMX7_ECSPI1_ADDR = 0x30820000, 215 FSL_IMX7_ECSPIn_SIZE = (4 * KiB), 216 217 /* AIPS-3 End */ 218 219 /* AIPS-2 Begin */ 220 221 FSL_IMX7_AXI_DEBUG_MON_ADDR = 0x307E0000, 222 FSL_IMX7_AXI_DEBUG_MON_SIZE = (64 * KiB), 223 224 FSL_IMX7_PERFMON2_ADDR = 0x307D0000, 225 FSL_IMX7_PERFMON1_ADDR = 0x307C0000, 226 FSL_IMX7_PERFMONn_SIZE = (64 * KiB), 227 228 FSL_IMX7_DDRC_ADDR = 0x307A0000, 229 FSL_IMX7_DDRC_SIZE = (4 * KiB), 230 231 FSL_IMX7_DDRC_PHY_ADDR = 0x30790000, 232 FSL_IMX7_DDRC_PHY_SIZE = (4 * KiB), 233 234 FSL_IMX7_TZASC_ADDR = 0x30780000, 235 FSL_IMX7_TZASC_SIZE = (64 * KiB), 236 237 FSL_IMX7_MIPI_DSI_ADDR = 0x30760000, 238 FSL_IMX7_MIPI_DSI_SIZE = (4 * KiB), 239 240 FSL_IMX7_MIPI_CSI_ADDR = 0x30750000, 241 FSL_IMX7_MIPI_CSI_SIZE = 0x4000, 242 243 FSL_IMX7_LCDIF_ADDR = 0x30730000, 244 FSL_IMX7_LCDIF_SIZE = 0x8000, 245 246 FSL_IMX7_CSI_ADDR = 0x30710000, 247 FSL_IMX7_CSI_SIZE = (4 * KiB), 248 249 FSL_IMX7_PXP_ADDR = 0x30700000, 250 FSL_IMX7_PXP_SIZE = 0x4000, 251 252 FSL_IMX7_EPDC_ADDR = 0x306F0000, 253 FSL_IMX7_EPDC_SIZE = (4 * KiB), 254 255 FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, 256 FSL_IMX7_PCIE_PHY_SIZE = (4 * KiB), 257 258 FSL_IMX7_SYSCNT_CTRL_ADDR = 0x306C0000, 259 FSL_IMX7_SYSCNT_CMP_ADDR = 0x306B0000, 260 FSL_IMX7_SYSCNT_RD_ADDR = 0x306A0000, 261 262 FSL_IMX7_PWM4_ADDR = 0x30690000, 263 FSL_IMX7_PWM3_ADDR = 0x30680000, 264 FSL_IMX7_PWM2_ADDR = 0x30670000, 265 FSL_IMX7_PWM1_ADDR = 0x30660000, 266 FSL_IMX7_PWMn_SIZE = (4 * KiB), 267 268 FSL_IMX7_FlEXTIMER2_ADDR = 0x30650000, 269 FSL_IMX7_FlEXTIMER1_ADDR = 0x30640000, 270 FSL_IMX7_FLEXTIMERn_SIZE = (4 * KiB), 271 272 FSL_IMX7_ECSPI4_ADDR = 0x30630000, 273 274 FSL_IMX7_ADC2_ADDR = 0x30620000, 275 FSL_IMX7_ADC1_ADDR = 0x30610000, 276 FSL_IMX7_ADCn_SIZE = (4 * KiB), 277 278 FSL_IMX7_AIPS2_CONF_ADDR = 0x305F0000, 279 FSL_IMX7_AIPS2_CONF_SIZE = (64 * KiB), 280 281 /* AIPS-2 End */ 282 283 /* AIPS-1 Begin */ 284 285 FSL_IMX7_CSU_ADDR = 0x303E0000, 286 FSL_IMX7_CSU_SIZE = (64 * KiB), 287 288 FSL_IMX7_RDC_ADDR = 0x303D0000, 289 FSL_IMX7_RDC_SIZE = (4 * KiB), 290 291 FSL_IMX7_SEMAPHORE2_ADDR = 0x303C0000, 292 FSL_IMX7_SEMAPHORE1_ADDR = 0x303B0000, 293 FSL_IMX7_SEMAPHOREn_SIZE = (4 * KiB), 294 295 FSL_IMX7_GPC_ADDR = 0x303A0000, 296 297 FSL_IMX7_SRC_ADDR = 0x30390000, 298 299 FSL_IMX7_CCM_ADDR = 0x30380000, 300 301 FSL_IMX7_SNVS_HP_ADDR = 0x30370000, 302 303 FSL_IMX7_ANALOG_ADDR = 0x30360000, 304 305 FSL_IMX7_OCOTP_ADDR = 0x30350000, 306 FSL_IMX7_OCOTP_SIZE = 0x10000, 307 308 FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, 309 FSL_IMX7_IOMUXC_GPR_SIZE = (4 * KiB), 310 311 FSL_IMX7_IOMUXC_ADDR = 0x30330000, 312 FSL_IMX7_IOMUXC_SIZE = (4 * KiB), 313 314 FSL_IMX7_KPP_ADDR = 0x30320000, 315 FSL_IMX7_KPP_SIZE = (4 * KiB), 316 317 FSL_IMX7_ROMCP_ADDR = 0x30310000, 318 FSL_IMX7_ROMCP_SIZE = (4 * KiB), 319 320 FSL_IMX7_GPT4_ADDR = 0x30300000, 321 FSL_IMX7_GPT3_ADDR = 0x302F0000, 322 FSL_IMX7_GPT2_ADDR = 0x302E0000, 323 FSL_IMX7_GPT1_ADDR = 0x302D0000, 324 325 FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, 326 FSL_IMX7_IOMUXC_LPSR_SIZE = (4 * KiB), 327 328 FSL_IMX7_WDOG4_ADDR = 0x302B0000, 329 FSL_IMX7_WDOG3_ADDR = 0x302A0000, 330 FSL_IMX7_WDOG2_ADDR = 0x30290000, 331 FSL_IMX7_WDOG1_ADDR = 0x30280000, 332 333 FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, 334 335 FSL_IMX7_GPIO7_ADDR = 0x30260000, 336 FSL_IMX7_GPIO6_ADDR = 0x30250000, 337 FSL_IMX7_GPIO5_ADDR = 0x30240000, 338 FSL_IMX7_GPIO4_ADDR = 0x30230000, 339 FSL_IMX7_GPIO3_ADDR = 0x30220000, 340 FSL_IMX7_GPIO2_ADDR = 0x30210000, 341 FSL_IMX7_GPIO1_ADDR = 0x30200000, 342 343 FSL_IMX7_AIPS1_CONF_ADDR = 0x301F0000, 344 FSL_IMX7_AIPS1_CONF_SIZE = (64 * KiB), 345 346 FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000, 347 FSL_IMX7_A7MPCORE_DAP_SIZE = (1 * MiB), 348 349 /* AIPS-1 End */ 350 351 FSL_IMX7_EIM_CS0_ADDR = 0x28000000, 352 FSL_IMX7_EIM_CS0_SIZE = (128 * MiB), 353 354 FSL_IMX7_OCRAM_PXP_ADDR = 0x00940000, 355 FSL_IMX7_OCRAM_PXP_SIZE = (32 * KiB), 356 357 FSL_IMX7_OCRAM_EPDC_ADDR = 0x00920000, 358 FSL_IMX7_OCRAM_EPDC_SIZE = (128 * KiB), 359 360 FSL_IMX7_OCRAM_MEM_ADDR = 0x00900000, 361 FSL_IMX7_OCRAM_MEM_SIZE = (128 * KiB), 362 363 FSL_IMX7_TCMU_ADDR = 0x00800000, 364 FSL_IMX7_TCMU_SIZE = (32 * KiB), 365 366 FSL_IMX7_TCML_ADDR = 0x007F8000, 367 FSL_IMX7_TCML_SIZE = (32 * KiB), 368 369 FSL_IMX7_OCRAM_S_ADDR = 0x00180000, 370 FSL_IMX7_OCRAM_S_SIZE = (32 * KiB), 371 372 FSL_IMX7_CAAM_MEM_ADDR = 0x00100000, 373 FSL_IMX7_CAAM_MEM_SIZE = (32 * KiB), 374 375 FSL_IMX7_ROM_ADDR = 0x00000000, 376 FSL_IMX7_ROM_SIZE = (96 * KiB), 377 }; 378 379 enum FslIMX7IRQs { 380 FSL_IMX7_USDHC1_IRQ = 22, 381 FSL_IMX7_USDHC2_IRQ = 23, 382 FSL_IMX7_USDHC3_IRQ = 24, 383 384 FSL_IMX7_UART1_IRQ = 26, 385 FSL_IMX7_UART2_IRQ = 27, 386 FSL_IMX7_UART3_IRQ = 28, 387 FSL_IMX7_UART4_IRQ = 29, 388 FSL_IMX7_UART5_IRQ = 30, 389 FSL_IMX7_UART6_IRQ = 16, 390 391 FSL_IMX7_ECSPI1_IRQ = 31, 392 FSL_IMX7_ECSPI2_IRQ = 32, 393 FSL_IMX7_ECSPI3_IRQ = 33, 394 FSL_IMX7_ECSPI4_IRQ = 34, 395 396 FSL_IMX7_I2C1_IRQ = 35, 397 FSL_IMX7_I2C2_IRQ = 36, 398 FSL_IMX7_I2C3_IRQ = 37, 399 FSL_IMX7_I2C4_IRQ = 38, 400 401 FSL_IMX7_USB1_IRQ = 43, 402 FSL_IMX7_USB2_IRQ = 42, 403 FSL_IMX7_USB3_IRQ = 40, 404 405 FSL_IMX7_GPT1_IRQ = 55, 406 FSL_IMX7_GPT2_IRQ = 54, 407 FSL_IMX7_GPT3_IRQ = 53, 408 FSL_IMX7_GPT4_IRQ = 52, 409 410 FSL_IMX7_GPIO1_LOW_IRQ = 64, 411 FSL_IMX7_GPIO1_HIGH_IRQ = 65, 412 FSL_IMX7_GPIO2_LOW_IRQ = 66, 413 FSL_IMX7_GPIO2_HIGH_IRQ = 67, 414 FSL_IMX7_GPIO3_LOW_IRQ = 68, 415 FSL_IMX7_GPIO3_HIGH_IRQ = 69, 416 FSL_IMX7_GPIO4_LOW_IRQ = 70, 417 FSL_IMX7_GPIO4_HIGH_IRQ = 71, 418 FSL_IMX7_GPIO5_LOW_IRQ = 72, 419 FSL_IMX7_GPIO5_HIGH_IRQ = 73, 420 FSL_IMX7_GPIO6_LOW_IRQ = 74, 421 FSL_IMX7_GPIO6_HIGH_IRQ = 75, 422 FSL_IMX7_GPIO7_LOW_IRQ = 76, 423 FSL_IMX7_GPIO7_HIGH_IRQ = 77, 424 425 FSL_IMX7_WDOG1_IRQ = 78, 426 FSL_IMX7_WDOG2_IRQ = 79, 427 FSL_IMX7_WDOG3_IRQ = 10, 428 FSL_IMX7_WDOG4_IRQ = 109, 429 430 FSL_IMX7_PCI_INTA_IRQ = 125, 431 FSL_IMX7_PCI_INTB_IRQ = 124, 432 FSL_IMX7_PCI_INTC_IRQ = 123, 433 FSL_IMX7_PCI_INTD_MSI_IRQ = 122, 434 435 FSL_IMX7_UART7_IRQ = 126, 436 437 #define FSL_IMX7_ENET_IRQ(i, n) ((n) + ((i) ? 100 : 118)) 438 439 FSL_IMX7_MAX_IRQ = 128, 440 }; 441 442 #endif /* FSL_IMX7_H */ 443