1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/intc/aspeed_intc.h" 19 #include "hw/misc/aspeed_scu.h" 20 #include "hw/adc/aspeed_adc.h" 21 #include "hw/misc/aspeed_sdmc.h" 22 #include "hw/misc/aspeed_xdma.h" 23 #include "hw/timer/aspeed_timer.h" 24 #include "hw/rtc/aspeed_rtc.h" 25 #include "hw/i2c/aspeed_i2c.h" 26 #include "hw/misc/aspeed_i3c.h" 27 #include "hw/ssi/aspeed_smc.h" 28 #include "hw/misc/aspeed_hace.h" 29 #include "hw/misc/aspeed_sbc.h" 30 #include "hw/misc/aspeed_sli.h" 31 #include "hw/watchdog/wdt_aspeed.h" 32 #include "hw/net/ftgmac100.h" 33 #include "target/arm/cpu.h" 34 #include "hw/gpio/aspeed_gpio.h" 35 #include "hw/sd/aspeed_sdhci.h" 36 #include "hw/usb/hcd-ehci.h" 37 #include "qom/object.h" 38 #include "hw/misc/aspeed_lpc.h" 39 #include "hw/misc/unimp.h" 40 #include "hw/misc/aspeed_peci.h" 41 #include "hw/fsi/aspeed_apb2opb.h" 42 #include "hw/char/serial-mm.h" 43 #include "hw/intc/arm_gicv3.h" 44 45 #define ASPEED_SPIS_NUM 3 46 #define ASPEED_EHCIS_NUM 4 47 #define ASPEED_WDTS_NUM 8 48 #define ASPEED_CPUS_NUM 4 49 #define ASPEED_MACS_NUM 4 50 #define ASPEED_UARTS_NUM 13 51 #define ASPEED_JTAG_NUM 2 52 53 struct AspeedSoCState { 54 DeviceState parent; 55 56 MemoryRegion *memory; 57 MemoryRegion *dram_mr; 58 MemoryRegion dram_container; 59 MemoryRegion sram; 60 MemoryRegion spi_boot_container; 61 MemoryRegion spi_boot; 62 MemoryRegion vbootrom; 63 AddressSpace dram_as; 64 AspeedRtcState rtc; 65 AspeedTimerCtrlState timerctrl; 66 AspeedI2CState i2c; 67 AspeedI3CState i3c; 68 AspeedSCUState scu; 69 AspeedSCUState scuio; 70 AspeedHACEState hace; 71 AspeedXDMAState xdma; 72 AspeedADCState adc; 73 AspeedSMCState fmc; 74 AspeedSMCState spi[ASPEED_SPIS_NUM]; 75 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 76 AspeedSBCState sbc; 77 AspeedSLIState sli; 78 AspeedSLIState sliio; 79 MemoryRegion secsram; 80 UnimplementedDeviceState sbc_unimplemented; 81 AspeedSDMCState sdmc; 82 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 83 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 84 AspeedMiiState mii[ASPEED_MACS_NUM]; 85 AspeedGPIOState gpio; 86 AspeedGPIOState gpio_1_8v; 87 AspeedSDHCIState sdhci; 88 AspeedSDHCIState emmc; 89 AspeedLPCState lpc; 90 AspeedPECIState peci; 91 SerialMM uart[ASPEED_UARTS_NUM]; 92 Clock *sysclk; 93 UnimplementedDeviceState iomem; 94 UnimplementedDeviceState video; 95 UnimplementedDeviceState emmc_boot_controller; 96 UnimplementedDeviceState dpmcu; 97 UnimplementedDeviceState pwm; 98 UnimplementedDeviceState espi; 99 UnimplementedDeviceState udc; 100 UnimplementedDeviceState sgpiom; 101 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; 102 AspeedAPB2OPBState fsi[2]; 103 }; 104 105 #define TYPE_ASPEED_SOC "aspeed-soc" 106 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 107 108 struct Aspeed2400SoCState { 109 AspeedSoCState parent; 110 111 ARMCPU cpu[ASPEED_CPUS_NUM]; 112 AspeedVICState vic; 113 }; 114 115 #define TYPE_ASPEED2400_SOC "aspeed2400-soc" 116 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) 117 118 struct Aspeed2600SoCState { 119 AspeedSoCState parent; 120 121 A15MPPrivState a7mpcore; 122 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */ 123 }; 124 125 #define TYPE_ASPEED2600_SOC "aspeed2600-soc" 126 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) 127 128 struct Aspeed27x0SoCState { 129 AspeedSoCState parent; 130 131 ARMCPU cpu[ASPEED_CPUS_NUM]; 132 AspeedINTCState intc[2]; 133 GICv3State gic; 134 MemoryRegion dram_empty; 135 }; 136 137 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc" 138 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC) 139 140 struct Aspeed10x0SoCState { 141 AspeedSoCState parent; 142 143 ARMv7MState armv7m; 144 }; 145 146 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" 147 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) 148 149 struct AspeedSoCClass { 150 DeviceClass parent_class; 151 152 /** valid_cpu_types: NULL terminated array of a single CPU type. */ 153 const char * const *valid_cpu_types; 154 uint32_t silicon_rev; 155 uint64_t sram_size; 156 uint64_t secsram_size; 157 int spis_num; 158 int ehcis_num; 159 int wdts_num; 160 int macs_num; 161 int uarts_num; 162 int uarts_base; 163 const int *irqmap; 164 const hwaddr *memmap; 165 uint32_t num_cpus; 166 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 167 bool (*boot_from_emmc)(AspeedSoCState *s); 168 }; 169 170 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); 171 172 enum { 173 ASPEED_DEV_VBOOTROM, 174 ASPEED_DEV_SPI_BOOT, 175 ASPEED_DEV_IOMEM, 176 ASPEED_DEV_UART0, 177 ASPEED_DEV_UART1, 178 ASPEED_DEV_UART2, 179 ASPEED_DEV_UART3, 180 ASPEED_DEV_UART4, 181 ASPEED_DEV_UART5, 182 ASPEED_DEV_UART6, 183 ASPEED_DEV_UART7, 184 ASPEED_DEV_UART8, 185 ASPEED_DEV_UART9, 186 ASPEED_DEV_UART10, 187 ASPEED_DEV_UART11, 188 ASPEED_DEV_UART12, 189 ASPEED_DEV_UART13, 190 ASPEED_DEV_VUART, 191 ASPEED_DEV_FMC, 192 ASPEED_DEV_SPI0, 193 ASPEED_DEV_SPI1, 194 ASPEED_DEV_SPI2, 195 ASPEED_DEV_EHCI1, 196 ASPEED_DEV_EHCI2, 197 ASPEED_DEV_EHCI3, 198 ASPEED_DEV_EHCI4, 199 ASPEED_DEV_VIC, 200 ASPEED_DEV_INTC, 201 ASPEED_DEV_INTCIO, 202 ASPEED_DEV_SDMC, 203 ASPEED_DEV_SCU, 204 ASPEED_DEV_ADC, 205 ASPEED_DEV_SBC, 206 ASPEED_DEV_SECSRAM, 207 ASPEED_DEV_EMMC_BC, 208 ASPEED_DEV_VIDEO, 209 ASPEED_DEV_SRAM, 210 ASPEED_DEV_SDHCI, 211 ASPEED_DEV_GPIO, 212 ASPEED_DEV_GPIO_1_8V, 213 ASPEED_DEV_RTC, 214 ASPEED_DEV_TIMER1, 215 ASPEED_DEV_TIMER2, 216 ASPEED_DEV_TIMER3, 217 ASPEED_DEV_TIMER4, 218 ASPEED_DEV_TIMER5, 219 ASPEED_DEV_TIMER6, 220 ASPEED_DEV_TIMER7, 221 ASPEED_DEV_TIMER8, 222 ASPEED_DEV_WDT, 223 ASPEED_DEV_PWM, 224 ASPEED_DEV_LPC, 225 ASPEED_DEV_IBT, 226 ASPEED_DEV_I2C, 227 ASPEED_DEV_PECI, 228 ASPEED_DEV_ETH1, 229 ASPEED_DEV_ETH2, 230 ASPEED_DEV_ETH3, 231 ASPEED_DEV_ETH4, 232 ASPEED_DEV_MII1, 233 ASPEED_DEV_MII2, 234 ASPEED_DEV_MII3, 235 ASPEED_DEV_MII4, 236 ASPEED_DEV_SDRAM, 237 ASPEED_DEV_XDMA, 238 ASPEED_DEV_EMMC, 239 ASPEED_DEV_KCS, 240 ASPEED_DEV_HACE, 241 ASPEED_DEV_DPMCU, 242 ASPEED_DEV_DP, 243 ASPEED_DEV_I3C, 244 ASPEED_DEV_ESPI, 245 ASPEED_DEV_UDC, 246 ASPEED_DEV_SGPIOM, 247 ASPEED_DEV_JTAG0, 248 ASPEED_DEV_JTAG1, 249 ASPEED_DEV_FSI1, 250 ASPEED_DEV_FSI2, 251 ASPEED_DEV_SCUIO, 252 ASPEED_DEV_SLI, 253 ASPEED_DEV_SLIIO, 254 ASPEED_GIC_DIST, 255 ASPEED_GIC_REDIST, 256 }; 257 258 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 259 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); 260 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); 261 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 262 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 263 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 264 const char *name, hwaddr addr, 265 uint64_t size); 266 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 267 unsigned int count, int unit0); 268 269 static inline int aspeed_uart_index(int uart_dev) 270 { 271 return uart_dev - ASPEED_DEV_UART0; 272 } 273 274 static inline int aspeed_uart_first(AspeedSoCClass *sc) 275 { 276 return aspeed_uart_index(sc->uarts_base); 277 } 278 279 static inline int aspeed_uart_last(AspeedSoCClass *sc) 280 { 281 return aspeed_uart_first(sc) + sc->uarts_num - 1; 282 } 283 284 #endif /* ASPEED_SOC_H */ 285